公开(公告)号：DE19821581A1

公开(公告)日：1999-01-07

申请号：DE19821581

申请日：1998-05-14

Applicant: IBM

Inventor： LOEFFLER PETER ,  PFEFFER ERWIN ,  PFLUEGER THOMAS ,  TAST HANS-WERNER

IPC: G11C8/16 ,  G11C7/00 ,  G11C5/02

Abstract: The matrix uses a quantity of memory cells, along with a process for storing data in one quantity and a process for calling data from another quantity. The quantity of memory allows the functionality of a cell with repeated write connections by means of a quantity of cells with simple write connection and allows multiple simultaneous write accesses. The information, which is contained in the quantity of memory, is presented through all the memories together. It can be retrieved by a read function, which records on a subset of the named quantity. Stored data have three subsets A,B and C, operated on by read and write functions. Writing access is accomplished in three steps. First the contents of all memory, which are not modified, are read. As next values are calculated in a way, which are to be entered in a subset B of the named quantity of memory. The contents and the values of the subset B together represent the desired result. Device for reading contents of subset C of data uses data stored jointly.

公开(公告)号：DE19636381C1

公开(公告)日：1998-03-12

申请号：DE19636381

申请日：1996-09-09

Applicant: IBM

Inventor： GOLDRIAN GOTTFRIED ,  TAST HANS-WERNER

IPC: G06F3/00 ,  G06F13/42 ,  G06F13/38

Abstract: The processor bus has two transmission lines which can be switched between a first operating mode in which the lines are arranged in two groups for transmission in opposite directions and a second operating mode in which both groups have the same transmission direction. The switching between the alternate operating modes is effected by switching the transmission direction of one of the bus line groups.