公开(公告)号：DE3579422D1

公开(公告)日：1990-10-04

申请号：DE3579422

申请日：1985-11-22

Applicant: IBM

Inventor： SHIBATA ICHIROH ,  WATANABE SHINPEI

IPC: G09G5/10 ,  G09G1/16 ,  G09G5/02 ,  G09G5/06 ,  G09G5/30 ,  G09G1/28

Abstract: The display system comprises a color map memory or palette circuit (30) with a plurality of registers (32) for converting a color code to a color video signal and a blinking circuit. The blinking circuit is composed of at least two blink color registers (46,48), a blink code register (50), and a blink control circuit (42). Prior to blinking, a processor loads the address of a palette register retaining a color to be blinked into the blink code register, loads a color video signal (e.g. 6-bit signal) representing the color to be blinked into a selected blink color register, and loads a color video signal representing a different color to be displayed alternately with the color to be blinked into the other blink color register. The control circuit alternately writes the contents of the blink color registers into the palette register specified by the address in the blink code register, in synchronization with a blink clock. Thus, a specified color and a different color are displayed alternately at dot positions of the specified color, to achieve color blinking.

公开(公告)号：DE3380042D1

公开(公告)日：1989-07-13

申请号：DE3380042

申请日：1983-12-15

Applicant: IBM

Inventor： TAJIMA SATOSHI ,  WATANABE SHINPEI ,  SUZUKI TOSHIO ,  YANAGI TSUTOMU ,  YONEMOCHI KENSHIN

IPC: G06F3/023 ,  G06F11/00 ,  H03M11/20

公开(公告)号：HK18690A

公开(公告)日：1990-03-16

申请号：HK18690

申请日：1990-03-08

Applicant: IBM

Inventor： TAJIMA SATOSHI ,  WATANABE SHINPEI ,  SUZUKI TOSHIO ,  YANAGI TSUTOMU ,  YONEMOCHI KENSHIN

IPC: G06F3/023 ,  G06F11/00 ,  H03M11/20

公开(公告)号：IN165132B

公开(公告)日：1989-08-19

申请号：IN506MA1985

申请日：1985-07-03

Applicant: IBM

Inventor： GOHDA YUJI ,  WATANABE SHINPEI

IPC: G09G5/36 ,  G06F3/153 ,  G09G1/14 ,  G09G5/08 ,  G09G1/16

Abstract: A window defining signal which has one state (e.g. high) during the scanning time corresponding to a window area of CRT screen is delayed for a predetermined time. Delayed window defining signal and non delayed window defining signal are XORed to determine time for energizing CRT to display a window borderline.

公开(公告)号：SG77144A1

公开(公告)日：2000-12-19

申请号：SG1997002951

申请日：1997-08-15

Applicant: IBM

Inventor： WATANABE SHINPEI ,  SUNAGA TOSHIO

IPC: G06F12/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096

Abstract: A DRAM system that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order so that a seamless operation is assured not only for reading but also for writing. A prefetch mechanism is used for reading and writing data to a separate memory array at an early stage, so that the activation and precharge operation, which must be performed before reading the next set of data from the memory array, does not affect nor cause any deterioration of access speed. The amount of data prefetched is twice as much as that fetched in the period represented by an array time constant so that in a single bank structure a seamless operation can be performed both for reading and for writing, even when row accesses are performed.

公开(公告)号：DE3586928T2

公开(公告)日：1993-07-15

申请号：DE3586928

申请日：1985-05-10

Applicant: IBM

Inventor： GOHDA YUJI ,  WATANABE SHINPEI

IPC: G09G5/36 ,  G06F3/153 ,  G09G1/14 ,  G09G5/08 ,  G09G1/16

Abstract: A window defining signal which has one state (e.g. high) during the scanning time corresponding to a window area of CRT screen is delayed for a predetermined time. Delayed window defining signal and non delayed window defining signal are XORed to determine time for energizing CRT to display a window borderline.

公开(公告)号：DE3586928D1

公开(公告)日：1993-02-11

申请号：DE3586928

申请日：1985-05-10

Applicant: IBM

Inventor： GOHDA YUJI ,  WATANABE SHINPEI

IPC: G09G5/36 ,  G06F3/153 ,  G09G1/14 ,  G09G5/08 ,  G09G1/16

Abstract: A window defining signal which has one state (e.g. high) during the scanning time corresponding to a window area of CRT screen is delayed for a predetermined time. Delayed window defining signal and non delayed window defining signal are XORed to determine time for energizing CRT to display a window borderline.

公开(公告)号：DE3585461D1

公开(公告)日：1992-04-09

申请号：DE3585461

申请日：1985-05-10

Applicant: IBM

Inventor： AOKI YUTAKA ROOM NO ,  WATANABE SHINPEI

IPC: G09G5/00 ,  G06F3/147 ,  G06F3/153 ,  G06T11/00 ,  G09G5/02 ,  G09G5/39 ,  G09G1/28 ,  G09G1/16

Abstract: A color image display apparatus includes an image memory comprising a plurality of memory planes, each corresponding to a specific color. The memory planes are simultaneously addressed by a common address from a CPU so as to either write image data on data busses respectively connected thereto or read image data out to these data busses. The apparatus also includes a read/write circuit comprising means for distributing the image data to be written in the image memory to the data bus of each memory plane, first selecting means for selecting one or more memory planes in which the image data are to be written, a plurality of read registers corresponding to the respective memory planes, and second selecting means for selecting one or more read registers whose contents are to be outputted to the CPU. In this apparatus, the write operation is performed in only a selected memory plane or planes while the read operation is performed in all of the memory planes simultaneously.

公开(公告)号：CA1236601A

公开(公告)日：1988-05-10

申请号：CA478046

申请日：1985-04-01

Applicant: IBM

Inventor： GOHDA YUJI ,  WATANABE SHINPEI

IPC: G09G5/36 ,  G06F3/153 ,  G09G1/14 ,  G09G5/08 ,  G09G1/00

Abstract: WINDOW BORDERLINE GENERATING CIRCUIT FOR CRT DISPLAY The disclosure teaches a circuit, for generating window borderlines for a CRT display, that is capable of generating such borderlines with a simple hardware configuration. A window region defining signal is generated which takes a first state for a period corresponding to a desired window region, and a second state for a period not corresponding to the window region during scanning period of the screen of CRT display. Then the signal is delayed and the delayed signal, and said window region defining signal, are exclusive-ORed to provide a timing signal for generating borderlines of the window.

公开(公告)号：CA1205205A

公开(公告)日：1986-05-27

申请号：CA439560

申请日：1983-10-24

Applicant: IBM

Inventor： TAJIMA SATOSHI ,  WATANABE SHINPEI

IPC: G06F3/02 ,  G06F3/023 ,  G06F11/00 ,  G06F11/14 ,  H04L7/00 ,  H04L7/04 ,  G06F3/03

Abstract: SERIAL KEYBOARD INTERFACE SYSTEM In data processing systems it has been proposed that a keyboard and a data processing unit be interconnected through a data line and a clock line so as to transmit keyboard outcodes bit-serially through the data line and to transmit a keyboard out clock signal through the clock line. This could result in false operation however due to noise being induced in the interconnecting cables from both the data and clock lines resulting in false operation and incorrect data being transmitted. The present invention which provides a serial keyboard interface system overcomes the problem of erroneous transmission of keyboard data due to noise pulses induced in the interconnecting lines. Data signals are generated at the data processing unit indicating whether the correct number of bits of a data frame are counted for the received signal. If incorrect number is received then the status signal which is returned to the keyboard causes a retransmission of the signal.