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公开(公告)号：DE2640414A1
公开(公告)日：1977-04-07
申请号：DE2640414
申请日：1976-09-08
Applicant: IBM
Inventor： ARPS RONALD BARTHOLD , BAHL LALIT RAI , WEINBERGER ARNOLD
IPC: H03M7/00 , G06T9/00 , H03M7/30 , H04B1/66 , H04N1/417 , H04N7/32 , H04N1/00 , H03K13/00 , G06F5/00
Abstract: An apparatus is disclosed for compressing a p x q image array of two-valued (black/white) sample points. The image array points are serially applied to the apparatus in consecutive raster scan lines. In response, the apparatus simultaneously forms two matrices respectively representing a high order p x q predictive error array and a p x q array of location events (such as the raster leading edges of all objects in the image). Improved compression is achieved by selecting between the more compression efficient of two methods for encoding the position of errors in the prediction error array. These alternative methods are conventional run-length coding and a novel form of reference encoding, used selectively but to significant advantage. Thus, a run-length compression codeword is formed from the count C of non-errors between consecutive errors (in response to the occurrence of each error in the jth bit position of the ith scan line of the predictive error array) upon either C T and there being no occurrence of a line difference encoding for the error (where i, j, C and T have positive integers). A line difference codeword with difference value v is generated upon the joint event of C>T and either the single or multiple occurrence of location events in the ith-1 scan line of the location event array within the bit position range of B
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公开(公告)号：DE2623986A1
公开(公告)日：1976-12-16
申请号：DE2623986
申请日：1976-05-28
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: Logic circuits in an adder for use in data processing for the detection of a sum of all ZEROES together with the mathematics upon which the circuits are based. Circuits and mathematics are also disclosed for a detection of a sum of all digits equal to the radix less one. Each of these detected sum conditions are produced prior to or at least concurrently with the production of the sum itself.
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公开(公告)号：GB1280753A
公开(公告)日：1972-07-05
申请号：GB5402870
申请日：1970-11-13
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: 1280753 Digital stores INTERNATIONAL BUSINESS MACHINES CORP 13 Nov 1970 [24 Dec 1969] 54028/70 Heading G4C Words in a store are addressed associatively and non-associatively. The non-associative part of the address defines a general category for the words being searched by addressing a corresponding part of the store. The category may be Addition for example, the corresponding part of the store containing the table for this function. The associative part of the address is searched within the addressed part of the store without regard to the actual store location. The embodiment described comprises a number of storage arrays 12-15 each comprising an 8 x 8 matrix of transistor bi-stable circuits defining 8 Î 4 storage cells. The pair of bi-stables forming a cell can take the states 1, 0 representing a 1-bit, 0, 1 representing a 0-bit, 0, 0 or or 1. The cells in array 12 contain the first bit only of each of a number of stored words, the second bits being in array 13. Arrays 14, 15 similarly store the first and second bits of other words. Register 25 contains an address including X and Y bits which define a general category of words by addressing a particular cell in each array. Bits S, together with the word M1, M0 in a mask register 27, define an associative search in the selected general category and whether or not the corresponding bit position is to be searched. Write mode.-S1, S0 are set to 1, 1 and M1, M0 to 00 (i.e. unmask). The X and Y bits having selected a cell in each array, one half of each such cell is selected for write-in by the output on 51, 55 of units 50, 54. Arrays 12, 13 or 14, 15 are selected by enabling line 62 or 63, first and second bits on lines 64, 65 being written in to the selected half of the cells in the respective selected arrays, e.g. 12 and 13. S1, S0 are now set to 0, 0 and the other half of each selected cell is set up by data signals on 64, 65. Read mode.-The sense amplifiers of arrays 12, 13 or 14, 15 are selected by enabling lines 68 or 69. Bits X, Y, S select the cells to be read in the selected arrays, the bit-state of the selected cell halves being passed to output lines 70. Search mode.-The X, Y bits define the category to be searched and the S bits define items to be searched associatively in the category. M is set to 00 (i.e. unmask). When S1 = 1 the addressed cells in arrays 12, 14 are searched for matching 1, 0 (1-bit) or 0, 0, (don't care), and when S1 = 0, for matching 0, 1 (0-bit) or 0, 0. Similarly SO causes a search in arrays 13, 15. Match detected in arrays 12 or 13 causes latch 73 to be set, match in arrays 14 or 15 latch 74.
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公开(公告)号：DE1962903A1
公开(公告)日：1970-07-30
申请号：DE1962903
申请日：1969-12-16
Applicant: IBM
Inventor： WEINBERGER ARNOLD
Abstract: 1,272,687. Adder; code converter; counter. INTERNATIONAL BUSINESS MACHINES CORP. 30 Dec., 1969 [15 Jan., 1969], No. 63205/69. Headings G4A and G4H. An adder, counter, code converter comprises a number of logic junction generators 22 arranged in a first set, 2 and 3, which is responsive to a group of parallel input signals A-E and in a second set, 6, 7 and 8, which is responsive only to groups of parallel output signals from the first set to produce a number of differently weighted parallel output signals X, Y and Z. The weighted output corresponds to the number of " 1 "s present on the input lines A-E. Circuit details.-A logic function generator 22a is shown in Fig. 5 and comprises a number of transistors 26a, 28a, 29a. Additional transistors may be provided (see generator 22) to handle additional inputs and further interconnections within each generator and between generators may be provided to produce the desired logic functions. Additional generators 22 may be added to Fig. 6 to allow 7 or more inputs to be handled. A clamp circuit 32 is provided to prevent the transistors 29 and 29a from saturating and the device is constructed on two semiconductor chips which constitute the first and second sets of logic generators. As an adder.-An adder comprising N 7- input devices may be used to add 7 N-bit numbers, each device having as inputs corresponding bits from each of the seven numbers. The three outputs from the device may be combined in a known three input adder. As a counter.-The weighted outputs X, Y, Z correspond to, and thus count, the number of " 1 "s on the inputs lines A-E. Various reduction ratios may be used (i.e. the ratio of the number of inputs to the number of outputs), e.g. 7 : 3 or 15 : 4. In the embodiment the outputs are weighted 1À2À4 so that 7 inputs are the largest that can be represented on 3 outputs. As a code converter.-The logic generators may be arranged to produce weighted outputs from a number of equi-valued and/or weighted inputs. Further details.-The notation used in Fig. 6, e.g. (A, B, C) [1, 3], is used to mean that a " 1 " signal is present if exactly 1 or 3 of the input signals, A, B, C are 1, and a " 0 " signal otherwise.
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公开(公告)号：DE1933935A1
公开(公告)日：1970-01-22
申请号：DE1933935
申请日：1969-07-04
Applicant: IBM
Inventor： WILLIAM BIDWELL ALEXANDER , WEINBERGER ARNOLD
Abstract: 1,220,000. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 7 July, 1969 [15 July, 1968], No. 34101/69. Heading H3T. [Also in Division G4] The bi-stable storage cell of Fig. 2 for use in a monolithic memory, is enabled for read, write or associative interrogation by pulses on leads X, Y to turn transistors 58 and 59 on and off respectively. For write, a pulse on lead 31 or 32 turns a respective transistor 54 or 55 on and an associated transistor 50 or 51 off. During read and interrogate, a pulse appears on lead 31 or 32 depending on the stored state. Leads 31, 32 go to a differential sense amplifier, an isolator circuit (Fig. 3, not shown) being connected in lead 31. The memory using the cells, stores each bit in true and inverse form in respective cells, but the two cells for a bit may both store 1, or both store 0.
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Patent Agency Ranking
公开(公告)号：DE3275689D1
公开(公告)日：1987-04-16
申请号：DE3275689
申请日：1982-03-09
Applicant: IBM
Inventor： FOGELL LEONARD LEWIS , LEVINE SAMUEL ROBERT , WEINBERGER ARNOLD
Abstract: This error checker determines if more than one set of control signals F1 through FN are on and also flags invalid as opposed to valid situations where none of the control signals F1 to FN are on. To distinguish the invalid from valid situations where none of the control signals F1 to FN are on, an additional control signal X = F1 · F2 ·...· FN is generated and then fed with the control signals F1 to FN through a prior art detector which detects when more than one or none of the control signals X and F1 through FN are on.
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公开(公告)号：CA1103359A
公开(公告)日：1981-06-16
申请号：CA314499
申请日：1978-10-27
Applicant: IBM
Inventor： GRICE DONALD G , JOHNSON DAVID F , WEINBERGER ARNOLD
Abstract: PROGRAMMABLE LOGIC ARRAY ADDER This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits Ai, Bi of two n digit binary numbers A0, A1....An-1 and Bo, B1....Bn-1 plus a carry Cin. The decoders generate an output signal called a min term on a different line for each of the four possible combinations AiBi, Ai?i, ?iBi and ?i?i of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product terms fP = f0(A0,B0) f1(A1,B1)....fn-1(An-1,Bn-1) fn(Cin) The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms fp. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an AND function to generate a sum bit Si that is an AND of two functions supplied by the OR array to the inputs of the latches to generate a sum S0, S1....Sn-1 plus a carry Cout for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an AND function.
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公开(公告)号：DE2800598A1
公开(公告)日：1978-07-13
申请号：DE2800598
申请日：1978-01-07
Applicant: IBM
Inventor： LEVINE SAMUEL ROBERT , SINGH SHANKER , WEINBERGER ARNOLD
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公开(公告)号：AU2101276A
公开(公告)日：1978-07-06
申请号：AU2101276
申请日：1976-12-31
Applicant: IBM
Inventor： BRYANT LOUIS RONALD , PEDERSEN RAYMOND JAMES , WEINBERGER ARNOLD
Abstract: A digital LRU network in which a use value in a chronology register always appears to be increasing; it is incremented for each access to a different data block currently represented in an active LRU array and this use value is copied into an index for that block in an active use-value array. Special circuits are provided to maintain the appearance of continuously increasing use values. At the start of each array search, the special circuits check the chronology register to determine if its use value is nearing its highest registerable value by testing its two high order bits for 1's. If so, the chronology register is set to 100...0, which is higher than any use value in the active array, after the use values in the active array are shifted one bit position to the right by writing them into corresponding positions in another array, which then becomes the active array. The right shift drops the low-order bit in the use values and sets the high-order bit to zero. The right shift increases the range of use values that can subsequently be set into the active array without affecting the stored relationships among the existing use values, and enables the incrementing of use values to continue. The second array is used to permit overlap of the read cycle of one array with the write cycle of the other array.
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