公开(公告)号：DE10110578A1

公开(公告)日：2001-10-18

申请号：DE10110578

申请日：2001-03-06

Applicant: IBM

Inventor： LEENSTRA JENS ,  MUELLER ANTJE ,  PILLE JUERGEN ,  WENDEL DIETER

IPC: G06F13/18 ,  G06F13/26

Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.

公开(公告)号：DE10110576A1

公开(公告)日：2001-10-11

申请号：DE10110576

申请日：2001-03-06

Applicant: IBM

Inventor： HOFSTEE PETER ,  LEENSTRA JENS ,  TAST HANS-WERNER ,  WENDEL DIETER

IPC: G01R31/3185 ,  G06F11/26

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

公开(公告)号：DE19908618A1

公开(公告)日：1999-10-14

申请号：DE19908618

申请日：1999-02-27

Applicant: IBM

Inventor： FUHRMANN HORST ,  WEDECK JOERG ,  WENDEL DIETER ,  WILLE UDO

IPC: G06F12/084 ,  G06F12/0855 ,  G06F12/08

Abstract: The system has a number of processors (PU) that form a multiprocessor system that have connections to a common cache memory (15) that serves as a buffer memory between the processors and the main memory (18). A highly efficient means of processing data is provided by subdividing the cache memory into a number of core modules (15-0---15-3). An Independent claim is included for method for high power buffering of instructions and data in cache memory of computer system.