公开(公告)号：DE19527592C2

公开(公告)日：2003-07-17

申请号：DE19527592

申请日：1995-07-28

Applicant: IBM

Inventor： TAST HANS WERNER ,  GETZLAFF KLAUS JOERG ,  WILLE UDO ,  MUENSTER HANS-JUERGEN

IPC: G06F12/0855 ,  G06F12/08

公开(公告)号：DE19908618A1

公开(公告)日：1999-10-14

申请号：DE19908618

申请日：1999-02-27

Applicant: IBM

Inventor： FUHRMANN HORST ,  WEDECK JOERG ,  WENDEL DIETER ,  WILLE UDO

IPC: G06F12/084 ,  G06F12/0855 ,  G06F12/08

Abstract: The system has a number of processors (PU) that form a multiprocessor system that have connections to a common cache memory (15) that serves as a buffer memory between the processors and the main memory (18). A highly efficient means of processing data is provided by subdividing the cache memory into a number of core modules (15-0---15-3). An Independent claim is included for method for high power buffering of instructions and data in cache memory of computer system.

公开(公告)号：FR2406851A1

公开(公告)日：1979-05-18

申请号：FR7828926

申请日：1978-10-02

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22 ,  G06F9/16

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：CH632349A5

公开(公告)日：1982-09-30

申请号：CH1001078

申请日：1978-09-26

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH ROLAND ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22

公开(公告)号：AU4085678A

公开(公告)日：1980-04-24

申请号：AU4085678

申请日：1978-10-19

Applicant: IBM

Inventor： BAZLEN DIETER ,  NEUBER SIEGFRIED ,  WILLE UDO ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ

IPC: G06F9/22 ,  G06F9/16

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：DE19614481A1

公开(公告)日：1997-10-16

申请号：DE19614481

申请日：1996-04-12

Applicant: IBM

Inventor： WILLE UDO ,  GETZLAFF KLAUS-JOERG ,  WITHELM BIRGIT ,  TAST HANS-WERNER

IPC: G06F12/0897 ,  G06F12/08 ,  G06F13/16 ,  G06F15/16

Abstract: The second order cache memory (L2) has a directory (9) which stores an address i and validity bit Vi(L1) for each of its memory sectors Yi. The value of each validity bit depends on whether the contents of sector Yi are also stored in the corresponding sector Zj of a first order cache memory (L1). Both cache memories store the V-, MC- and C-bits used for MESI cache protocol.

公开(公告)号：FR2406851B1

公开(公告)日：1986-04-11

申请号：FR7828926

申请日：1978-10-02

Applicant: IBM

Inventor： BAZLEN DIETER ,  BERGER ROLF ,  BLUM ARNOLD ,  BOCK DIETRICH W ,  CHILINSKI HERBERT ,  GENG HELLMUTH R ,  HAJDU JOHANN ,  IRRO FRITZ ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

公开(公告)号：DE2747304A1

公开(公告)日：1979-04-26

申请号：DE2747304

申请日：1977-10-21

Applicant: IBM DEUTSCHLAND

Inventor： BAZLEN DIETER DIPL ING DR ,  BERGER ROLF DIPL ING ,  BLUM ARNOLD DIPL ING ,  BOCK DIETRICH DIPL ING ,  CHILINSKI HERBERT DIPL ING ,  GENG HELLMUTH ROLAND ,  HAJDU JOHANN ,  IRRO FRITZ DIPL ING ,  NEUBER SIEGFRIED ,  WILLE UDO

IPC: G06F9/22 ,  G06F9/16 ,  G06F13/06

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.