公开(公告)号：DE102004024661A1

公开(公告)日：2005-12-15

申请号：DE102004024661

申请日：2004-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN ,  HIRLER FRANZ ,  HAEBERLEN OLIVER

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

Abstract: The method involves back-forming a first layer (DOX) in the upper trench region (30o), the filing (40) serving as a mask. The semiconductor material (20) on the side walls of the trench in the upper region of the trench are back-formed, with the first layer serving as a mask. A new semiconductor material (20n) of defined doping (p) is formed on the back-formed trench side walls near the upper trench region, forming a channel region of defined doping (p).

公开(公告)号：DE10354421A1

公开(公告)日：2005-06-30

申请号：DE10354421

申请日：2003-11-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOTEK MANFRED ,  RIEGER WALTER ,  HAEBERLEN OLIVER

IPC: H01L21/336 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

Abstract: A process for producing a gate contact structure during the production of a trench high power transistor, comprises preparing a semiconductor substrate, forming a trench in the substrate, precipitating a gate dielectric (1) onto the inner walls of the trench, and precipitating a field oxide. The gate oxide is precipitated followed by a gate material (3). The gate material is then polyrecess etched. The liner (4) is then precipitated, and the liner and the intermediate oxide (5) are selectively etched. The liner consists of silicon nitride or oxynitride.