公开(公告)号：JP2006157016A

公开(公告)日：2006-06-15

申请号：JP2005342830

申请日：2005-11-28

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： POELZL MARTIN

IPC: H01L29/78 ,  H01L29/739

CPC classification number: H01L29/66727 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66143 ,  H01L29/66348 ,  H01L29/66734

Abstract: PROBLEM TO BE SOLVED: To provide a simple semiconductor device improved in precision, and having a contact hole, and also to provide the method of manufacturing the same.
SOLUTION: Each of a plurality of trenches (2) isolated by each mesa region (3), and an electrode (4) insulated at each trench (2) from a semiconductor substrate (1) by a first insulating layer (6) are provided on the semiconductor substrate (1). The front surfaces (7, 8, and 9) of a structure in which the upper limit of the electrode is located at level deeper than the upper limit of the trench are subjected to a thermal oxidation process. This forms a second insulating layer (10) covering at least a part of the front surface of the structure. A planarization process is carried out such that the semiconductor substrate (1) is exposed in the mesa region (3). After the planarization process, a contact hole (12) is formed in the mesa region (3) using the residual portion of the second insulating layer (10) as a contact hole mask.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供精度提高并具有接触孔的简单的半导体器件，并且还提供其制造方法。 解决方案：由每个台面区域（3）隔离的多个沟槽（2）中的每一个以及通过第一绝缘层（6）与半导体衬底（1）在每个沟槽（2）处绝缘的电极（4） ）设置在半导体基板（1）上。 其中电极的上限位于比沟槽上限更深的结构的前表面（7,8和9）进行热氧化处理。 这形成了覆盖结构的前表面的至少一部分的第二绝缘层（10）。 进行平面化处理，使得半导体衬底（1）暴露在台面区域（3）中。 在平坦化处理之后，使用第二绝缘层（10）的残留部分作为接触孔掩模，在台面区域（3）中形成接触孔（12）。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE102004024661B4

公开(公告)日：2006-04-13

申请号：DE102004024661

申请日：2004-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN ,  HIRLER FRANZ ,  HAEBERLEN OLIVER

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

Abstract: The method involves back-forming a first layer (DOX) in the upper trench region (30o), the filing (40) serving as a mask. The semiconductor material (20) on the side walls of the trench in the upper region of the trench are back-formed, with the first layer serving as a mask. A new semiconductor material (20n) of defined doping (p) is formed on the back-formed trench side walls near the upper trench region, forming a channel region of defined doping (p).

公开(公告)号：DE102005046480A1

公开(公告)日：2006-04-06

申请号：DE102005046480

申请日：2005-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN ,  RIEGER WALTER

IPC: H01L21/336 ,  H01L29/78

Abstract: The method involves applying an auxiliary layer (110) on a semiconductor substrate, and structuring the layer (110) for forming a trench (114) that extends to the substrate and includes opposed side walls (115). A single crystalline semiconductor layer (132) is formed at one of the walls. An insulated gate electrode (140) is fabricated on the side walls of the trench and the substrate opposite to the layer (132). An independent claim is also included for a vertical MOS transistor comprising a gate electrode.

公开(公告)号：DE102004024659A1

公开(公告)日：2005-12-15

申请号：DE102004024659

申请日：2004-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIEGER WALTER ,  HIRLER FRANZ ,  POELZL MARTIN ,  KOTEK MANFRED

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L29/73 ,  H01L29/78

公开(公告)号：DE10350684A1

公开(公告)日：2005-06-09

申请号：DE10350684

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN ,  HIRLER FRANZ ,  HAEBERLEN OLIVER ,  KOTEK MANFRED ,  RIEGER WALTER

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: Production of a power transistor arrangement comprises forming a cell field (3) in a semiconductor substrate, inserting cell field trenches (5) and a connecting trench (6) within the cell field, forming an insulating layer, applying a first conducting layer on the insulating layer, applying a conducting auxiliary layer, forming a gate electrode structure in the cell field trenches, and forming a contact of the field electrode structure in the region of the connecting trenches connected to the cell field trenches. An independent claim is also included for a power transistor arrangement produced by the above process.

公开(公告)号：DE10212149A1

公开(公告)日：2003-10-16

申请号：DE10212149

申请日：2002-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENNINGER RALF ,  HIRLER FRANZ ,  KRUMREY JOACHIM ,  RIEGER WALTER ,  POELZL MARTIN

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.

公开(公告)号：DE10350684B4

公开(公告)日：2008-08-28

申请号：DE10350684

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN ,  HIRLER FRANZ ,  HAEBERLEN OLIVER ,  KOTEK MANFRED ,  RIEGER WALTER

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: Production of a power transistor arrangement comprises forming a cell field (3) in a semiconductor substrate, inserting cell field trenches (5) and a connecting trench (6) within the cell field, forming an insulating layer, applying a first conducting layer on the insulating layer, applying a conducting auxiliary layer, forming a gate electrode structure in the cell field trenches, and forming a contact of the field electrode structure in the region of the connecting trenches connected to the cell field trenches. An independent claim is also included for a power transistor arrangement produced by the above process.

公开(公告)号：DE10208787B4

公开(公告)日：2007-04-26

申请号：DE10208787

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRIZA WOLFGANG ,  SCHAEFFER CARSTEN ,  POELZL MARTIN

IPC: H01L21/74 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/334 ,  H01L21/336 ,  H01L21/763 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/8249

公开(公告)号：DE102005041256A1

公开(公告)日：2007-03-01

申请号：DE102005041256

申请日：2005-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HIRLER FRANZ ,  ZUNDEL MARKUS ,  POELZL MARTIN ,  ZELSACHER RUDOLF

IPC: H01L29/78 ,  H01L21/336

Abstract: Embedded in a trench structure (3) and electrically insulated against a semiconductor body (2) by an insulating structure (5), an electrode structure has a gate electrode structure (4 1) and a field electrode structure (4 2) fitted beneath the gate electrode structure and electrically insulated by it. An independent claim is also included for a method for producing a trench transistor.

公开(公告)号：DE102004057237A1

公开(公告)日：2006-06-01

申请号：DE102004057237

申请日：2004-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN

IPC: H01L29/423 ,  H01L21/334 ,  H01L29/78

Abstract: Second insulation layer (10) is produced, covering at least part of the surface (7, 8, 9) of the structure. This is achieved by subjecting the surface of the structure to a thermal oxidation process. A planarization process is then carried out, in such a way that the semiconductor body (1) is laid bare in the region of the mesa zones (3). The contact holes (12) are formed in the mesa zones, using the second insulation layer remaining after the planarization process as a contact hole mask. An independent claim is included for the corresponding structure.