公开(公告)号：DE102008058974A1

公开(公告)日：2010-04-29

申请号：DE102008058974

申请日：2008-11-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BACHER ERWIN ,  BEHRENDT ANDREAS ,  ORTNER JOERG ,  RIEGER WALTER ,  ZELSACHER RUDOLF ,  ZUNDEL MARKUS

IPC: H01L29/06 ,  H01L29/40

公开(公告)号：DE102005046480A1

公开(公告)日：2006-04-06

申请号：DE102005046480

申请日：2005-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN ,  RIEGER WALTER

IPC: H01L21/336 ,  H01L29/78

Abstract: The method involves applying an auxiliary layer (110) on a semiconductor substrate, and structuring the layer (110) for forming a trench (114) that extends to the substrate and includes opposed side walls (115). A single crystalline semiconductor layer (132) is formed at one of the walls. An insulated gate electrode (140) is fabricated on the side walls of the trench and the substrate opposite to the layer (132). An independent claim is also included for a vertical MOS transistor comprising a gate electrode.

公开(公告)号：DE102004024659A1

公开(公告)日：2005-12-15

申请号：DE102004024659

申请日：2004-05-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIEGER WALTER ,  HIRLER FRANZ ,  POELZL MARTIN ,  KOTEK MANFRED

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L29/73 ,  H01L29/78

公开(公告)号：DE102004009323A1

公开(公告)日：2005-09-22

申请号：DE102004009323

申请日：2004-02-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIEGER WALTER

IPC: H01L21/336 ,  H01L29/78

Abstract: The vertical diffusion metal oxide semiconductor (DMOS) transistor has active trenches (4) and vertical drift zones (8) under the gate electrode (2) and pillar connection (1), with an implanted contact (9) for an electrical connection with the pillar. In the event of an avalanche, the breakthrough is below the trenches, and the avalanche flow path is at the trench centers. A silicon table (5) is between the trenches, without a contact hole/polyplug structure.

公开(公告)号：DE10350684A1

公开(公告)日：2005-06-09

申请号：DE10350684

申请日：2003-10-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN ,  HIRLER FRANZ ,  HAEBERLEN OLIVER ,  KOTEK MANFRED ,  RIEGER WALTER

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: Production of a power transistor arrangement comprises forming a cell field (3) in a semiconductor substrate, inserting cell field trenches (5) and a connecting trench (6) within the cell field, forming an insulating layer, applying a first conducting layer on the insulating layer, applying a conducting auxiliary layer, forming a gate electrode structure in the cell field trenches, and forming a contact of the field electrode structure in the region of the connecting trenches connected to the cell field trenches. An independent claim is also included for a power transistor arrangement produced by the above process.

公开(公告)号：DE10212149A1

公开(公告)日：2003-10-16

申请号：DE10212149

申请日：2002-03-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENNINGER RALF ,  HIRLER FRANZ ,  KRUMREY JOACHIM ,  RIEGER WALTER ,  POELZL MARTIN

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L27/105

Abstract: The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.

公开(公告)号：DE102004009083B4

公开(公告)日：2008-08-07

申请号：DE102004009083

申请日：2004-02-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HIRLER FRANZ ,  WEBER HANS ,  RIEGER WALTER ,  POELZL MARTIN ,  HENNINGER RALF

IPC: H01L29/78 ,  H01L21/336

公开(公告)号：DE10353387B4

公开(公告)日：2008-07-24

申请号：DE10353387

申请日：2003-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOTEK MANFRED ,  HAEBERLEN OLIVER ,  POELZL MARTIN ,  RIEGER WALTER

IPC: H01L21/336 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

Abstract: In the case of the cost-effective method according to the invention for fabricating a power transistor arrangement, a trench power transistor arrangement ( 1 ) is fabricated with four patterning planes each containing a lithography step. The power transistor arrangement according to the invention has a cell array ( 3 ) with cell array trenches ( 5 ) each containing a field electrode structure ( 11 ) and a gate electrode structure ( 10 ). The field electrode structure ( 11 ) is electrically conductively connected to the source metallization ( 15 ) by a connection trench ( 6 ) in the cell array ( 3 ).

公开(公告)号：DE10214175B4

公开(公告)日：2006-06-29

申请号：DE10214175

申请日：2002-03-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POELZL MARTIN ,  RIEGER WALTER ,  HENNINGER RALF ,  HIRLER FRANZ

IPC: H01L21/336 ,  H01L21/225 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45

公开(公告)号：DE10345494A1

公开(公告)日：2005-05-04

申请号：DE10345494

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RIEGER WALTER

IPC: H01L21/683 ,  H01L21/68

Abstract: The processing method has the semiconductor substrate supported within an electrostatic or magnetic chuck (9), such that its front surface faces the chuck, for permanent application of an electrically conductive metal foil, e.g. of Cu or Al, to its rear surface, for acting as an electrical contact, heat sink or mechanical stabilizer. An independent claim for a semiconductor with one or more semiconductor elements having a thickness of less than 200 microns is also included.