公开(公告)号：DE10026276B4

公开(公告)日：2006-02-16

申请号：DE10026276

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN ,  SCHAFFROTH THILO

IPC: G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: The explicit high voltage source (1) and internal low voltage source (2) are selectively connected to respective connection areas (4,5) of a programmable fuse (3) by respective connectors (6,7). The switches (8,9) connect the connectors to the connection areas, when a control signal is applied to the switches from a controller (16), to apply required voltage.

公开(公告)号：DE10306620A1

公开(公告)日：2004-09-09

申请号：DE10306620

申请日：2003-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FRANKOWSKY GERD ,  KAISER ROBERT

IPC: G01R19/165 ,  G01R31/28 ,  H01L23/544 ,  H01L21/66 ,  H01L23/58

Abstract: A switching device (4) selects one of several internal voltages (V0-Vn) for testing according to a selection signal. A comparator device (5) compares a test voltage dependent on the selected internal voltage with an externally preset reference voltage (VREF) and issues an error signal as a result. An independent claim is also included for a method for testing an integrated circuit with a test circuit.

公开(公告)号：DE50002130D1

公开(公告)日：2003-06-18

申请号：DE50002130

申请日：2000-01-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G06F11/20 ,  G11C29/00

公开(公告)号：FR2823901A1

公开(公告)日：2002-10-25

申请号：FR0204923

申请日：2002-04-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

IPC: G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/40 ,  G11C29/44

Abstract: A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.

公开(公告)号：DE10063684A1

公开(公告)日：2002-07-18

申请号：DE10063684

申请日：2000-12-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  KAISER ROBERT

IPC: G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  H01L23/525

Abstract: A circuit configuration for driving a programmable link has a drive circuit for the selection and blowing of the fuse, and also a shift register, by which an activation signal can be fed to the drive circuit. In order to provide the data to be blown, in a preferred embodiment, a volatile memory cell may be provided. The present circuit configuration enables the blowing of fuses and thus repair of defective memory cells in mass memories even after encapsulation of a chip having the mass memory. Moreover, the shift register described effectively prevents impermissibly high currents from being able to occur as a result of simultaneous blowing of too many fuses.

公开(公告)号：DE10031946A1

公开(公告)日：2002-01-17

申请号：DE10031946

申请日：2000-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAFFROTH THILO

IPC: G11C7/10 ,  G11C7/22 ,  G11C29/02 ,  H03K5/08 ,  H03K5/153 ,  H03K5/135

Abstract: The timing circuit (2) is connected to a selection circuit (3) that provides a control signal (TM). A regulatable current source (4) in the timing circuit receives the control signal producing a timing output signal (ST) with a delay with respect to a reference time. An Independent claim is also included for method of producing an output signal in timing circuit.

公开(公告)号：DE10006236C2

公开(公告)日：2001-12-20

申请号：DE10006236

申请日：2000-02-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT ,  KRASSER HANS-JUERGEN

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  H03K5/13 ,  H03K5/131 ,  H03K5/133 ,  G01R31/3187 ,  H03K5/14

Abstract: In the configuration, the module can "learn" one or more time intervals from the external tester and then repeat them internally or compare them to its own internally measured time intervals, for instance, for the purpose of evaluating whether the module in question has crossed a time specification value or remains below the value. The module can also measure and store one or more internal time intervals and transmit them to the external tester in digital or analog form.

公开(公告)号：DE10026251A1

公开(公告)日：2001-12-06

申请号：DE10026251

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT ,  SCHAMBERGER FLORIAN

IPC: G11C17/16 ,  H01L23/525 ,  H01L27/105 ,  G11C17/14

Abstract: The fuse or anti-fuse programming device uses application of an electrical voltage (V1-V2) for destruction of the fuse or anti-fuse (1), with the latter connected in series between the source-drain paths of at least 2 transistors (T1,T2), e.g. a p-channel FET and a n-channel FET positioned on opposite sides of the fuse.

公开(公告)号：DE10026243A1

公开(公告)日：2001-12-06

申请号：DE10026243

申请日：2000-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  LINDOLF JUERGEN ,  SCHNEIDER HELMUT

IPC: G11C17/00 ,  G11C17/18 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/66 ,  H01L23/525 ,  G11C29/00

Abstract: The fuse state read-out method uses application of a voltage (Vblh) to the fuse which has a reduced voltage level relative to an internal voltage (Vint) of the semiconductor memory device, e.g. a voltage level which is reduced by between 20 and 30 % relative to an internal voltage of about 2 V, for defining the high potential of the bit lines (BL) of the memory cell field (6).

公开(公告)号：DE10004648A1

公开(公告)日：2001-08-09

申请号：DE10004648

申请日：2000-02-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOHNSON BRET A ,  KAISER ROBERT

IPC: G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/407 ,  G11C7/00

Abstract: A drive circuit (3) has an input (31) connected to output (23) of a read amplifier (2) to which the input (DQ) is fed through input line (21). The drive circuit is operated with respect to the output (RD0) of amplifiers. Output (32) of circuit (3) is connected to a signaling line (4), to which a precharging circuit (5) is connected. A memory (6) is connected to signal line. A connection line (7) outputs control signal to amplifier and circuits (5,6).