公开(公告)号：MXPA02007602A

公开(公告)日：2003-01-28

申请号：MXPA02007602

申请日：2001-01-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G06K17/00 ,  G07F7/10 ,  G07F7/12 ,  H04L9/32

Abstract: La invencion se refiere a un procedimiento y a un dispositivo para la autenticacion mutua de dos unidades procesadores de datos. La autenticacion mutua de dos unidades procesadores de datos se realiza normalmente en dos autenticaciones sucesivas separadas. Normalmente se usa un metodo reto-respuesta (challenge-response). Un primer reto se transmite desde una primera unidad procesadora de datos (1), a una segunda unidad procesadora de datos (2) que envia una primera respuesta, de acuerdo a la invencion, se genera una segunda respuesta por medio de la primera unidad procesadora de datos (1) y se transmite a la segunda unidad procesadora de datos (2).

公开(公告)号：DE10130099A1

公开(公告)日：2003-01-02

申请号：DE10130099

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAIL MARKUS ,  HESS ERWIN ,  POCKRANDT WOLFGANG ,  WEDEL ARMIN

IPC: G07F7/10 ,  H04L9/32 ,  G07F7/08

Abstract: The invention relates to a challenge-response device (1) comprising an input (5) for receiving a challenge signal from a terminal and an output (6) for emitting a response signal. The challenge-response device (1) also comprises a feedback shift register (2), a memory (3) for saving a state of the feedback shift register and a unit (8), which applies an old shift register state corresponding to a previous challenge-response operation to the feedback shift register, in order to generate a new shift register state, which corresponds to a current challenge-response operation, from the old shift register state. An arithmetic unit (4) calculates the response signal using the new shift register state and the challenge signal and emits said response signal via the output (6) to the terminal for verification.

公开(公告)号：ES2178783T3

公开(公告)日：2003-01-01

申请号：ES97932758

申请日：1997-07-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZELLNER ANGELA ,  RAESCHMEIER ANDREAS ,  POCKRANDT WOLFGANG

IPC: H01L21/822 ,  G06F1/00 ,  G06F12/14 ,  G06F21/87 ,  H01L23/525 ,  H01L23/544 ,  H01L23/58 ,  H01L27/04

Abstract: A semiconductor circuit, in particular for use in an integrated module, has at least one operational assembly with a drive circuit, such as a microprocessor, and a data memory. The semiconductor circuit has at least one initialization assembly for testing and/or for initializing the operational assembly. A disconnectable connecting line connects the operational assembly to the initialization assembly. In order to increase reliability, the initialization assembly is permanently disconnected from the operational assembly, by disconnecting the connecting lines, after the semiconductor circuit has been completed. In order to make it more difficult to reactivate the disconnected connecting lines, the semiconductor circuit has a potential line connected to the initialization assembly and/or to the operational assembly in a region of the connecting line. The initialization assembly and/or the operational assembly are configured in such a way that, when the potential line is connected to the connecting line, the initialization assembly is placed in an inactive state.

公开(公告)号：ES2174480T3

公开(公告)日：2002-11-01

申请号：ES98943695

申请日：1998-07-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG ,  SEDLAK HOLGER ,  VIEHMANN HANS-HEINRICH

IPC: G11C16/04 ,  G11C16/06

Abstract: The invention relates to a semiconductor memory having a non-volatile two-transistor memory cell which has an N-channel selection transistor and an N-channel memory transistor. The drive circuitry for the cell includes a P-channel transfer transistor. A transfer channel is connected to a row line leading to the memory cell. This enables the voltages required for programming to be obtained with relatively little technological complexity.

公开(公告)号：AT221221T

公开(公告)日：2002-08-15

申请号：AT98931907

申请日：1998-04-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G06F1/00 ,  G06F12/14 ,  G06F15/16 ,  G06F21/44 ,  H04L29/06

Abstract: The system checks whether authorization exists for at least two data processing devices to exchange data with one another. In the preferred embodiment, both data processing devices are of identical design. Check data are simultaneously produced, in response to a trigger signal, in both data processing devices. The check data are compared with one another in the data processing device to which a control function has been allocated.

公开(公告)号：ES2170518T3

公开(公告)日：2002-08-01

申请号：ES98941267

申请日：1998-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G07F7/08 ,  G07F7/12 ,  G07F19/00

Abstract: The invention relates to a data carrier (CC) for storing units of value (VALUE) credited by a credit station (T1) and debited in at least one debit station (T2). Upon completion of the crediting procedure, the data carrier contains an identification number (T1ID) of the crediting station (T1) which is transmitted to the debiting station (T2) when the unit of value (VALUE) is debited. The debiting station (T2) uses the identification number (T1ID) to check if the units of value (VALUE) have been credited by an authorized crediting station (T1).

公开(公告)号：BR0015796A

公开(公告)日：2002-07-23

申请号：BR0015796

申请日：2000-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ALLINGER ROBERT ,  POCKRANDT WOLFGANG

IPC: G06M3/12 ,  G07F7/08 ,  G07F7/10 ,  H03K21/40

Abstract: A method for operating a multistage counter in only one counting direction is described. The counting value of a single-stage auxiliary counter that can be changed in only one counting direction is changed in predetermined counting values of the multistage counter. The respective counting value states of the multistage counter and of the single-stage auxiliary counter are registered. First authenticity data is generated by logically linking the counting value of the auxiliary counter to supplementary data.

公开(公告)号：DE59802556D1

公开(公告)日：2002-01-31

申请号：DE59802556

申请日：1998-07-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G07F7/08 ,  G07F7/12 ,  G07F19/00

Abstract: The invention relates to a data carrier (CC) for storing units of value (VALUE) credited by a credit station (T1) and debited in at least one debit station (T2). Upon completion of the crediting procedure, the data carrier contains an identification number (T1ID) of the crediting station (T1) which is transmitted to the debiting station (T2) when the unit of value (VALUE) is debited. The debiting station (T2) uses the identification number (T1ID) to check if the units of value (VALUE) have been credited by an authorized crediting station (T1).

公开(公告)号：DE59801598D1

公开(公告)日：2001-10-31

申请号：DE59801598

申请日：1998-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： POCKRANDT WOLFGANG

IPC: G07F7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10

Abstract: A method for reliably changing the value of a data medium having at least two volatile memory areas for storing a currently valid value. Each memory area has at least one associated nonvolatile control memory cell whose state defines the currently valid memory area. The current value is first written to an invalid memory area. A previously valid memory area and the associated control memory cell are then erased simultaneously and the control memory cell for the memory area to which information had previously been written is programmed, likewise simultaneously, so that the latter memory area can be recognized as the valid memory area.

公开(公告)号：AT470285T

公开(公告)日：2010-06-15

申请号：AT02751002

申请日：2002-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAIL MARKUS ,  HESS ERWIN ,  POCKRANDT WOLFGANG ,  WEDEL ARMIN

IPC: H04L9/32 ,  G07F7/08 ,  G07F7/10 ,  H03K3/84