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    Method for repairing hardware faults in memory components of a data processor
    22.
    发明专利
    Method for repairing hardware faults in memory components of a data processor 未知

    公开(公告)号：DE10120670A1

    公开(公告)日：2002-11-07

    申请号：DE10120670

    申请日：2001-04-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUCKERBAUER HERMANN ,  SCHAMBERGER FLORIAN

    IPC: G11C29/00

    Abstract: The repair of bit errors in memory components (7) with numerous memory cells detects the bit errors by an error recognition algorithm, and determines the address of the faulty memory cells. The bit errors are corrected by activating redundant memory cells, such that the correction takes place in an incorporated state of the memory component. Preferably, the memory components, in incorporated state, are fitted on a support, or a socket and are thus integrated in a data processor.

    23.
    发明专利
    未知

    公开(公告)号：FR2823901A1

    公开(公告)日：2002-10-25

    申请号：FR0204923

    申请日：2002-04-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

    IPC: G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/40 ,  G11C29/44

    Abstract: A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.

    24.
    发明专利
    未知

    公开(公告)号：DE10063684A1

    公开(公告)日：2002-07-18

    申请号：DE10063684

    申请日：2000-12-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAMBERGER FLORIAN ,  KAISER ROBERT

    IPC: G11C17/16 ,  G11C17/18 ,  G11C29/00 ,  H01L23/525

    Abstract: A circuit configuration for driving a programmable link has a drive circuit for the selection and blowing of the fuse, and also a shift register, by which an activation signal can be fed to the drive circuit. In order to provide the data to be blown, in a preferred embodiment, a volatile memory cell may be provided. The present circuit configuration enables the blowing of fuses and thus repair of defective memory cells in mass memories even after encapsulation of a chip having the mass memory. Moreover, the shift register described effectively prevents impermissibly high currents from being able to occur as a result of simultaneous blowing of too many fuses.

    28.
    发明专利
    未知

    公开(公告)号：DE102004062885B4

    公开(公告)日：2007-10-18

    申请号：DE102004062885

    申请日：2004-12-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAMBERGER FLORIAN ,  SOMMER MICHAEL BERNHARD ,  BAENISCH ANDREAS

    IPC: H01R12/04 ,  H01L23/50 ,  H01R13/20 ,  H05K1/18

    Abstract: Fastener (1) has a carrier element (2) and multitude of fastening elements (3). The fastening elements are arranged on the carrier element and comprises in each case an oblong body, which protrudes from carrier element and possesses a suitable form between further fastening elements for engaging and/or hooking. Fastening elements and carrier element are electrically conductive on their surface. Independent claims are also included for the following: (A) Electronic component; (B) Arrangement with an electronic conductor board and a semiconductor unit; and (C) Procedure for fastening semiconductor unit on an electronic conductor board.

    29.
    发明专利
    未知

    公开(公告)号：FR2823901B1

    公开(公告)日：2006-05-12

    申请号：FR0204923

    申请日：2002-04-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN

    IPC: G01R31/28 ,  G11C29/00 ,  G11C29/12 ,  G11C29/40 ,  G11C29/44

    Abstract: A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.

    30.
    发明专利
    未知

    公开(公告)号：DE59911513D1

    公开(公告)日：2005-03-03

    申请号：DE59911513

    申请日：1999-05-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

    IPC: H01L21/60 ,  G01R31/02 ,  G01R31/316 ,  H01L21/66 ,  H01L23/485

    Abstract: A bonding pad test configuration for establishing whether or not a semiconductor chip is bonded. The test configuration has a circuit that evaluates a state of a bond between a bonding wire and the bonding pad and is able to activate and deactivate operating and test modes depending on the bond state established. To this end, the bonding pad is divided into at least two parts, so that the circuit produced in the semiconductor chip itself can use signals derived from the parts of the bonding pad to establish whether or not the bonding wire is in contact with the parts.

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