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    21.
    发明专利
    未知

    公开(公告)号：DE10115880B4

    公开(公告)日：2007-01-25

    申请号：DE10115880

    申请日：2001-03-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： POECHMUELLER PETER ,  ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL

    IPC: G01R31/28 ,  G11C29/56 ,  G11C29/48

    Abstract: Test circuit for testing a synchronous memory circuit having a frequency multiplication circuit which multiplies a clock frequency of a low-frequency clock signal received from an external test unit by a particular frequency multiplication factor a test data generator which produces test data on the basis of data control signals received from the external test unit and outputs them to a data output driver a first signal delay circuit for delaying the test data which are output by the test data generator by an adjustable first delay time, a second signal delay circuit for delaying data which are read out of the synchronous memory circuit and are received by a data input driver in the test circuit by an adjustable second delay time, and having a data comparison circuit which compares the test data produced by the test data generator with the data read out of the memory circuit and, on the basis of the comparison result, outputs an indicator signal to the external test unit which indicates whether the synchronous memory circuit to be tested is operable.

    22.
    发明专利
    未知

    公开(公告)号：DE10034855B4

    公开(公告)日：2006-05-11

    申请号：DE10034855

    申请日：2000-07-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUPKE JENS ,  MUELLER JOCHEN ,  POECHMUELLER PETER ,  SCHITTENHELM MICHAEL

    IPC: G01R31/3183 ,  G01R31/3177 ,  G01R31/319 ,  G11C29/00 ,  G11C29/48 ,  H01L21/66

    Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

    23.
    发明专利
    未知

    公开(公告)号：DE10121309B4

    公开(公告)日：2004-01-29

    申请号：DE10121309

    申请日：2001-05-02

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： POECHMUELLER PETER ,  ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL

    IPC: G01R31/319 ,  G11C29/48 ,  G11C29/00 ,  G01R31/3193

    Abstract: Test circuit for testing a circuit to be tested, having a test data generator, which generates test data in a manner dependent on data control signals which are received via data control lines from an external test unit, a data output driver for outputting the generated test data via data line pairs of a differential data bus to the circuit to be tested, a data input circuit for receiving data that are read from the circuit to be tested and transmitted via the data line pairs of the differential data bus, a data comparison circuit, which compares the generated data and the read-out data and, in a manner depend at on the comparison result transmits an indication signal, which indicates whether the circuit to be tested is functional, to the external test unit via an indication signal line.

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