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公开(公告)号：WO03021604A3
公开(公告)日：2003-08-14
申请号：PCT/DE0203058
申请日：2002-08-21
Applicant: INFINEON TECHNOLOGIES AG , CORDES ERIC , EGGERS GEORG ERHARD , LUEPKE JENS , STOCKEN CHRISTIAN
Inventor： CORDES ERIC , EGGERS GEORG ERHARD , LUEPKE JENS , STOCKEN CHRISTIAN
CPC classification number: G11C29/50012 , G11C7/1051 , G11C7/1087 , G11C11/401 , G11C29/50
Abstract: The invention relates to a test method for testing, on a testing device (PA), semiconductor devices (P) that have a bi-directional data strobe link for a data strobe signal (DQS) whereby the data strobe signal is tested by transferring data between the semiconductor memory device (P) to be tested and a second semiconductor memory device of the same type (R). The invention also relates to a device for carrying out the inventive method.
Abstract translation: 用于测试半导体存储器件的方法和装置。 本发明涉及一种用于半导体存储器件的测试方法（P），具有用于一个数据选通信号（DQS）的双向数据选通端，在一个测试装置（PA），数据选通信号的由（要被检查的半导体存储器件之间的数据传送的测试 P）和相同类型的（R）的第二半导体存储器设备中进行，以及用于其的装置。
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公开(公告)号：DE10111440C2
公开(公告)日：2003-02-20
申请号：DE10111440
申请日：2001-03-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER , ERNST WOLFGANG , KRAUSE GUNNAR , KUHN JUSTUS , LUEPKE JENS , MUELLER JOCHEN , SCHITTENHELM MICHAEL
Abstract: An address generator is provided for generating addresses for testing an addressable circuit. The address generator can include a base address register for buffer-storing a base address. The base address register can be assigned an associated offset register group having a plurality of offset registers for buffer-storing relative address values. Further, the address generator can include a first multiplexer circuit which is dependent on a base register selection control signal, switches through an address buffer-stored in the base address register to a first input of an addition circuit and to an address bus, which is connected to the circuit to be tested. A second multiplexer circuit can be dependent on the base register selection control signal, through-connects the offset register group associated with the through-connected base address register to a third multiplexer circuit, which is dependent on an offset register selection control signal.
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公开(公告)号：DE10122619C1
公开(公告)日：2003-02-13
申请号：DE10122619
申请日：2001-05-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ERNST WOLFGANG , KRAUSE GUNNAR , KUHN JUSTUS , LUEPKE JENS , MUELLER JOCHEN , POECHMUELLER PETER , SCHITTENHELM MICHAEL
IPC: G01R31/319 , G01R31/3193 , G01R31/3183 , G11C29/00
Abstract: Test circuit for testing a synchronous circuit (3) which is clocked with an operating clock signal with a high operating clock frequency, having: (a) a frequency multiplication circuit (8), which receives a clock signal from an external test unit (2) and multiplies the low clock frequency of said clock signal by a specific factor for the purpose of generating the operating clock signal; (b) a data comparison circuit (49), which is clocked with the operating clock signal, receives a data block read from the synchronous circuit (3) to be tested, which data block has a specific number (n) of data words n each comprising m data bits, and compares it with associated desired data words, each comprising m desired data, for the purpose of generating a corresponding number (n) of error data words each comprising m error data; (c) a data register array (56), which has a plurality of data registers for buffer-storing the error data words generated; (d) a first error compression circuit (58), which logically ORs the error data words buffer-stored in the data register array (56) to form a compressed error data word comprising m error bit [sic], which is buffer-stored in an error register; (e) and having a second error compression circuit (60), which logically ORs the m error data contained in the compressed error data word to form an indication datum, the indication datum being output to the external test unit (2) with the low clock frequency, and indicating whether at least one data error has occurred in the data block read from the synchronous circuit (3) to be tested.
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公开(公告)号：DE50112029D1
公开(公告)日：2007-03-29
申请号：DE50112029
申请日：2001-06-28
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ERNST WOLFGANG , KRAUSE GUNNAR , KUHN JUSTUS , LUEPKE JENS , MUELLER JOCHEN , POECHMUELLER PETER , SCHITTENHELM MICHAEL
IPC: G11C29/00 , G01R31/3183 , G11C29/10
Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.
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公开(公告)号：DE10115880A1
公开(公告)日：2002-10-17
申请号：DE10115880
申请日：2001-03-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER , ERNST WOLFGANG , KRAUSE GUNNAR , KUHN JUSTUS , LUEPKE JENS , MUELLER JOCHEN , SCHITTENHELM MICHAEL
Abstract: The test circuit (1) has a has a frequency multiplier circuit (4), a test data generator (16), a first signal delay circuit (19), a second signal delay circuit (24) and a data comparison circuit (27) that compares the generated test data with data read from the memory circuit (3) and depending on the result outputs a display signal to the external test device (2) indicating whether the memory circuit being tested is functional.
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Patent Agency Ranking
公开(公告)号：DE10034900A1
公开(公告)日：2002-02-07
申请号：DE10034900
申请日：2000-07-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ERNST WOLFGANG , KRAUSE GUNNAR , KUHN JUSTUS , LUEPKE JENS , MUELLER JOCHEN , POECHMUELLER PETER , SCHITTENHELM MICHAEL
IPC: G01R31/319 , G11C29/48 , G11C29/56 , G01R31/3187 , G11C29/00
Abstract: The test system has build outside self test (BOST) module (10) that has a switching unit (11) for switching between the normal operation mode and BOST register programming operation mode based on the output of a switching criteria detector (11a). The switching criteria detector determines the switching criteria for the changeover switching. During normal operation mode, the BOST module controls a device under test (DUT) (20). During BOST register programming operation mode, the registered content of a register unit (12) are programmed. The BOST module is inserted into the signal path between a test device and the DUT. The register unit, algorithmic and logic unit (13), non-register driven logic unit (14) and DUT interface (15) in the BOST module receive the signal conditions (D1-D4) preset by the test device to generate test signals (D10) which are transmitted to the DUT. After receiving response signals from the DUT, the register unit is programmed to file constants and variables for generating test signals and evaluating the DUT. An Independent claim is also included for the use of the test system.
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公开(公告)号：DE10024875A1
公开(公告)日：2001-11-29
申请号：DE10024875
申请日：2000-05-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor： HAAS HERMANN , LUEPKE JENS
Abstract: A component holder for testing electronic components having a carrier, at least one component socket arranged on the carrier and having a group of component contacts to accommodate and make contact with a component, and at least one group of adapter contacts, which are arranged in a predefined standard arrangement on the carrier and are connected to the component contacts.
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公开(公告)号：DE10034897B4
公开(公告)日：2004-08-05
申请号：DE10034897
申请日：2000-07-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： ERNST WOLFGANG , KRAUSE GUNNAR , KUHN JUSTUS , LUEPKE JENS , MUELLER JOCHEN , POECHMUELLER PETER , SCHITTENHELM MICHAEL
IPC: G11C29/56 , G11C29/00 , G01R31/3183
Abstract: The address counter includes n programmable and/or fixed offset-registers (1-4) connected to selecting and logic circuits (5-8) for selecting the address offset values (a,b,c,d) stored in the offset registers and generating high frequency output addresses of the digital circuit under test. A control circuit receives m low-frequency input signals from the test equipment and generates n high frequency control signals for driving the selecting and logic circuits.
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公开(公告)号：DE10293994D2
公开(公告)日：2004-07-22
申请号：DE10293994
申请日：2002-08-21
Applicant: INFINEON TECHNOLOGIES AG
Inventor： CORDES ERIC , EGGERS GEORG ERHARD , LUEPKE JENS , STOCKEN CHRISTIAN
Abstract: A test method for a semiconductor memory device having a bidirectional data strobe terminal for a data strobe signal, and having at least one data terminal for a data signal at a test apparatus, which can at least generate data strobe and data signals and also transfer and evaluate data signals. The memory device is connected to a test apparatus, which generates data strobe and data signals, and transfers and evaluates data signals. In the course of the test using the data strobe and data signals, data are transferred from the first semiconductor memory device to a second semiconductor memory device of identical type and are evaluated after a read-out from the second semiconductor memory device by the test apparatus.
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公开(公告)号：DE10111440A1
公开(公告)日：2002-10-24
申请号：DE10111440
申请日：2001-03-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor： POECHMUELLER PETER , ERNST WOLFGANG , KRAUSE GUNNAR , KUHN JUSTUS , LUEPKE JENS , MUELLER JOCHEN , SCHITTENHELM MICHAEL
Abstract: The address generator has at least one base address register for temporarily storing a base address associated with an offset register group (13a..), first, second and third multiplexer circuits (38,17,25) and an addition circuit (60) that adds an address applied to a first input with a relative address applied to a second input to an address that is temporarily stored in the base address register.
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