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31 records (took 0.023 seconds)

    21.
    发明专利
    未知

    公开(公告)号：DE19931240A1

    公开(公告)日：2001-01-25

    申请号：DE19931240

    申请日：1999-07-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HAMAN ULRICH ,  WALLSTAB STEFAN

    IPC: G06K19/077 ,  H01L23/498 ,  H05K1/18

    Abstract: The invention relates to a multilayered chip card consisting of superimposed laminated foils (1, 2, 3), one of which is a flexible chip (1) fitted with an electronic circuit having the lateral dimensions of the entire chip card.

    22.
    发明专利
    未知

    公开(公告)号：DE50010098D1

    公开(公告)日：2005-05-25

    申请号：DE50010098

    申请日：2000-01-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WALLSTAB STEFAN

    IPC: G01R31/317 ,  G06K19/073

    Abstract: The circuit has at least one once-only switchable circuit element (1) whose switching state determines accessibility to a test mode. The circuit element may consist of a fusible bridge connected in series with an ignition transistor. A sense transistor may be connected in parallel with the ignition transistor to form a voltage divider, which is connected to an edge detector, such as a bi-stable flip-flop.

    23.
    发明专利
    未知

    公开(公告)号：AT291754T

    公开(公告)日：2005-04-15

    申请号：AT02762274

    申请日：2002-05-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ECKSTEIN GERNOT ,  AUMUELLER CHRISTIAN ,  WALLSTAB STEFAN

    IPC: G06F1/00 ,  G06F21/75 ,  G06F21/76 ,  H04L9/10

    Abstract: In a digital circuit comprising an asynchronous circuit, the supply voltage of the asynchronous circuit is varied by means of a random voltage jitter. The random variation of the supply voltage causes a time jitter in the processing of the individual operations within the asynchronous circuit, whereby an artificial synchronizing of individual measurements in side channel attacks is prevented.

    26.
    发明专利
    未知

    公开(公告)号：AT234472T

    公开(公告)日：2003-03-15

    申请号：AT99948884

    申请日：1999-09-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PALM HERBERT ,  SMOLA MICHAEL ,  WALLSTAB STEFAN

    IPC: H01L21/822 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  H01L21/82 ,  H01L27/04

    Abstract: The inventive circuit configuration has a plurality of function blocks (FB1...FBn), each function block being connected to at least one of the other function blocks and at least a portion of these connections being provided in the form of an interlocking element (SFF1...SFFm), which can be switched from normal mode to a test mode by means of an activation line (scan enable) and which has an additional data input and data output. These additional data inputs and data outputs are interconnected by data line sections (DL1...DLl) in such a way that the interlocking elements (SFF1...SFFm) form a shift register, which in turn forms a scan path. At least one electrically programmable fuse element (SE) is arranged along the activation line (scan enable) and/or the data line sections (DL1...DLl). This fuse element either interrupts the line concerned or connects it with a defined potential.

    27.
    发明专利
    未知

    公开(公告)号：DE59903326D1

    公开(公告)日：2002-12-12

    申请号：DE59903326

    申请日：1999-05-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SEDLAK HOLGER ,  SOEHNE PETER ,  SMOLA MICHAEL ,  WALLSTAB STEFAN

    IPC: G06F1/00 ,  G06F7/00 ,  G06F7/72 ,  G06F21/55 ,  G06F21/75 ,  G06K19/073 ,  H04L9/06

    Abstract: The method involves providing data for an encoding or decoding in an encoding- or decoding step which is selected from several alternative, equivalent encoding- or decoding steps, and/or which consists of several sequentially processed encoding- or decoding steps. The selected encoding- or decoding step is selected at random, and/or the encoding- or decoding steps are changed at random. An operand is preferably supplied at a suitable place with a random number, and at a further suitable place, a corresponding compensation operand is supplied with the same random number.

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