公开(公告)号：DE112014000056T5

公开(公告)日：2014-12-11

申请号：DE112014000056

申请日：2014-01-10

Applicant: INTEL CORP

Inventor： ALI ISAAC ,  PINSON KEITH ,  COWLEY NICHOLAS P ,  SUETINOV VIATCHESLAV I

IPC: H03M1/12

Abstract: Eine Vorrichtung und ein Verfahren der Analog-Digital-Wandlung mit sukzessiver Approximation für Empfänger, umfassend während eines Abtastmodus die Verbindung eines Kondensator-Arrays mit einer Vielzahl von Abtastschaltern, die mit einer Vielzahl verstärkter Eingangssignale gekoppelt sind, und während eines Wandlungsmodus die gemeinsame Verbindung des Kondensator-Arrays mit einem Komparator und Isolierung des Kondensator-Arrays von der Vielzahl von Abtastschaltern. Außerdem erfolgt eine Filterung durch Summierung der Abtastungen bei Phasen-Offsets.

公开(公告)号：DE602006000532D1

公开(公告)日：2008-03-27

申请号：DE602006000532

申请日：2006-08-04

Applicant: INTEL CORP

Inventor： SAWYER DAVID ALBERT ,  COWLEY NICHOLAS PAUL ,  ALI ISAAC

IPC: H03K5/13 ,  H03K5/00 ,  H03K5/135 ,  H03K5/15 ,  H03K5/156 ,  H03L7/081 ,  H03L7/18

Abstract: A pulse generator is provided for generating pulses with a selectable variable width and/or delay. The pulse generator comprises an oscillator (3) and a selecting arrangement for selecting how many of a first group (13) of delay elements are connected in series for delaying the oscillator signal (IF clock). Identical delay elements (26) are connected in series to form a second group, whose input receives the oscillator signal (IF clock). A measuring circuit (27) repeatedly measures the delay provided by the second group, for example providing output pulses (IP) whose width or duration (IPD) is equal to the delay. A reference pulse generator (29,30) generates a series of reference pulses (RP), each of which is of a predetermined duration equal to a fraction of the oscillator signal (IF clock) period. A control circuit, such as a charge pump and integrator (28), compares the measurement pulses (IP) and the reference pulses (RP) to generate an error signal which is fed back to timing delay control inputs of all of the delay elements such that the widths of the measurement and reference pulses (IP,RP) are made substantially equal to each other.