公开(公告)号：DE112011104552T5

公开(公告)日：2013-09-19

申请号：DE112011104552

申请日：2011-11-09

Applicant: INTEL CORP

Inventor： NEIGER GILBERT ,  PATEL BAIJU V ,  DIXON MARTIN G ,  COKE JAMES S ,  CROSSLAND JAMES B

IPC: G06F9/30 ,  G06F9/06

Abstract: Ausführungsformen von Systemen, Vorrichtungen und Verfahren zum Durchführen privilegierter agnostischer Lese- oder Schreibbefehle für Segmentbasisregister werden beschrieben. Ein beispielhaftes Verfahren kann Einholen des privilegierten agnostischen Schreibbefehls für Segmentbasisregister einschließen, wobei der privilegierte agnostische Schreibbefehl einen 64-Bit-Datenquelloperanden, Dekodieren des eingeholten privilegierten agnostischen Schreibbefehls für Segmentbasisregister und Ausführen des dekodierten privilegierten agnostischen Schreibbefehls für Segmentbasisregister einschließt, um die 64-Bit-Daten des Quelloperanden in das Segmentbasisregister zu schreiben, das durch den Opcode des privilegierten agnostischen Schreibbefehls für Segmentbasisregister identifiziert wird.

公开(公告)号：GB2499758A

公开(公告)日：2013-08-28

申请号：GB201310309

申请日：2011-11-09

Applicant: INTEL CORP

Inventor： PATEL BAIJU V ,  NEIGER GILBERT ,  DIXON MARTIN G ,  COKE JAMES S ,  CROSSLAND JAMES B

IPC: G06F9/30 ,  G06F9/34

Abstract: Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.

公开(公告)号：GB2465125B

公开(公告)日：2012-08-08

申请号：GB201003693

申请日：2008-08-28

Applicant: INTEL CORP

Inventor： KAUSHKI SHIVNANDAN ,  TIRUVALLUR KESHAVAN K ,  CROSSLAND JAMES B ,  MUTHRASANALLUR SRIDHAR ,  PARTHASARATHY RAJESH S ,  HOOD LUKE P

IPC: G06F13/24

Abstract: In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.

公开(公告)号：DE112008002402T5

公开(公告)日：2010-07-15

申请号：DE112008002402

申请日：2008-08-28

Applicant: INTEL CORP

Inventor： KAUSHKI SHIVNANDAN D ,  TIRUVALLUR KESHAVAN K ,  CROSSLAND JAMES B ,  MUTHRASANALLUR SRIDHAR ,  PARTHASARATHY RAJESH ,  HOOD LUKE P

IPC: G06F13/24

公开(公告)号：GB2449749B

公开(公告)日：2010-03-03

申请号：GB0809264

申请日：2008-05-22

Applicant: INTEL CORP

Inventor： FALIK OHAD ,  FRIEDMAN BEN-ZION ,  DOWECK JACOB D ,  WEISSMANN ELIEZER ,  CROSSLAND JAMES B

IPC: G06F12/10

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

公开(公告)号：DE102008025476A1

公开(公告)日：2008-12-18

申请号：DE102008025476

申请日：2008-05-28

Applicant: INTEL CORP

Inventor： FALIK OHAD ,  FRIEDMAN BEN-ZION ,  DOWECK JACOB D ,  WEISSMANN ELIEZER ,  CROSSLAND JAMES B

IPC: G06F12/10

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.