公开(公告)号：US20230298126A1

公开(公告)日：2023-09-21

申请号：US17699059

申请日：2022-03-18

Applicant: INTEL CORPORATION

Inventor： Sven Woop ,  Carsten Benthin ,  Prasoonkumar Surti ,  Joshua Barczak ,  Abhishek R. Appu ,  Pawel Majewski

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/10 ,  G06T15/06 ,  G06F12/0862 ,  G06F12/0811

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/10 ,  G06T15/06 ,  G06F12/0862 ,  G06F12/0811

Abstract: Apparatus and method for prefetching node data. For example, one embodiment of an apparatus comprises: ray tracing acceleration hardware to manage active ray tracing stack allocations within a traversal stack; and stack management hardware logic to issue a prefetch operation comprising an indication of bounding volume hierarchy (BVH) node data to be prefetched and an indication of a cache level, wherein responsive to performing the prefetch operation, the BVH node data is to be prefetched to the indicated cache level.

公开(公告)号：US11748841B2

公开(公告)日：2023-09-05

申请号：US17871781

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  Dukhwan Kim

IPC: G06T1/20 ,  G06N3/063 ,  G06F9/46 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06N3/044

CPC classification number: G06T1/20 ,  G06F9/46 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/044 ,  G06N3/084

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning. A method of embodiments, as described herein, includes limiting execution of workloads for the respective contexts of a plurality of contexts to a specified subset of a plurality of processing resources of a processing system according to physical resource slices of the processing system that are associated with the respective contexts of the plurality of contexts.

公开(公告)号：US11748606B2

公开(公告)日：2023-09-05

申请号：US17317857

申请日：2021-05-11

Applicant: INTEL CORPORATION

Inventor： Kamal Sinha ,  Balaji Vembu ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Farshad Akhbari ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Nadathur Rajagopalan Satish ,  John C. Weast ,  Mike B. MacPherson ,  Linda L. Hurd ,  Vasanth Ranganathan ,  Sanjeev S. Jahagirdar

IPC: G06F7/50 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20 ,  G06F9/30 ,  G06T15/00 ,  G06F15/78 ,  G06F15/76 ,  G06F1/3287 ,  G06F1/3293 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06T1/60

CPC classification number: G06N3/063 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/76 ,  G06F15/78 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/08 ,  G06N3/084 ,  G06T1/20 ,  G06T15/005 ,  G06T1/60

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230215400A1

公开(公告)日：2023-07-06

申请号：US18179067

申请日：2023-03-06

Applicant: Intel Corporation

Inventor： Louis Feng ,  Altug Koker ,  Tomasz Janczak ,  Andrew T. Lauritzen ,  David M. Cimini ,  Nikos Kaburlasos ,  Joydeep Ray ,  John H. Feit ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Devan Burke ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek R. Appu

IPC: G09G5/00 ,  G09G5/391 ,  G09G5/38 ,  G06T1/20 ,  G09G5/36

CPC classification number: G09G5/005 ,  G06T1/20 ,  G09G5/001 ,  G09G5/38 ,  G09G5/363 ,  G09G5/391 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2360/125

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

公开(公告)号：US11688122B2

公开(公告)日：2023-06-27

申请号：US17591166

申请日：2022-02-02

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00 ,  G06F9/48 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

CPC classification number: G06T15/005 ,  G06F9/4881 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US11636831B2

公开(公告)日：2023-04-25

申请号：US17383644

申请日：2021-07-23

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Tapan A. Ganpule ,  Anupama A. Thaploo ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G09G5/393 ,  G09G5/399 ,  G06F13/40 ,  G09G5/02 ,  G09G5/37 ,  G09G5/34 ,  H03K19/00 ,  H03K19/08 ,  G06F3/14 ,  G09G5/36

Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220413899A1

公开(公告)日：2022-12-29

申请号：US17358882

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  James Valerio ,  Joydeep Ray ,  Abhishek R. Appu ,  Alan Curtis ,  Prathamesh Raghunath Shinde ,  Brandon Fliflet ,  Ben J. Ashbaugh ,  John Wiegert

IPC: G06F9/48 ,  G06F9/38 ,  G06T1/20

Abstract: An apparatus to facilitate barrier state save and restore for preemption in a graphics environment is disclosed. The apparatus includes processing resources to execute a plurality of execution threads that are comprised in a thread group (TG) and mid-thread preemption barrier save and restore hardware circuitry to: initiate an exception handling routine in response to a mid-thread preemption event, the exception handling routine to cause a barrier signaling event to be issued; receive indication of a valid designated thread status for a thread of a thread group (TG) in response to the barrier signaling event; and in response to receiving the indication of the valid designated thread status for the thread of the TG, cause, by the thread of the TG having the valid designated thread status, a barrier save routine and a barrier restore routine to be initiated for named barriers of the TG.

公开(公告)号：US20220398101A1

公开(公告)日：2022-12-15

申请号：US17848559

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06F9/38 ,  G06F9/46 ,  G06T1/20 ,  G06F9/52 ,  G06F9/48 ,  G06F9/54 ,  G06F15/16 ,  G06F9/50 ,  G06F15/76 ,  G06F12/0897 ,  G06F12/0866 ,  G06T1/60

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

公开(公告)号：US20220357945A1

公开(公告)日：2022-11-10

申请号：US17834482

申请日：2022-06-07

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G09G5/393 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: One embodiment provides a graphics processor comprising a memory controller and a graphics processing resource coupled with the memory controller. The graphics processing resource includes circuitry configured to execute an instruction to perform a matrix operation on first input including weight data and second input including input activation data, generate intermediate data based on a result of the matrix operation, quantize the intermediate data to a floating-point format determined based on a statistical distribution of first output data, and output, as second output data, quantized intermediate data in a determined floating-point format.

公开(公告)号：US11494968B2

公开(公告)日：2022-11-08

申请号：US17322677

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Srivallaba Mysore ,  Subhajit Dasgupta ,  Hiroshi Akiba ,  Eric J. Hoekstra ,  Linda L. Hurd ,  Travis T. Schluessler ,  Daren J. Schmidt

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/20 ,  G06F1/3287 ,  G06F9/54

Abstract: Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.