公开(公告)号：US20190028710A1

公开(公告)日：2019-01-24

申请号：US15815759

申请日：2017-11-17

Applicant: INTEL CORPORATION

Inventor： Fangwen Fu ,  Jason Tanner ,  Satya N. Yedidi

IPC: H04N19/146 ,  H04N19/51

Abstract: The present techniques include deriving a threshold to maintain an encoding bitrate and determining a percentage of change of a current frame N based on an impact to a bitrate budget. The present techniques also include marking a reference frame N−1 as non-referenceable in response to the percentage of change being smaller than the threshold and encoding a static portion of frame N as a skip and encoding a non-static portion of frame N by referencing the reference frame N−1. Finally, the present techniques include overwriting a surface of the reference frame N with portions of the reference frame N−1 that have changed as compared to frame N.

公开(公告)号：US20190020872A1

公开(公告)日：2019-01-17

申请号：US15651620

申请日：2017-07-17

Applicant: Intel Corporation

Inventor： Fangwen Fu ,  Srinivasan Embar Raghukrishnan ,  Atthar H. Mohammed

IPC: H04N19/124 ,  H04N19/52 ,  H04N19/176

CPC classification number: H04N19/124 ,  G06F17/11 ,  H04N19/103 ,  H04N19/147 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52

Abstract: Systems, apparatus and methods are described including operations for video coding rate control including Rate Distortion Optimized Quantization on a block-by-block basis.

公开(公告)号：US20180041770A1

公开(公告)日：2018-02-08

申请号：US15483146

申请日：2017-04-10

Applicant: INTEL CORPORATION

Inventor： James M. Holland ,  Fangwen Fu ,  Satya N. Yedidi ,  Srinivasan Embar Raghukrishnan

IPC: H04N19/52 ,  H04N19/159 ,  H04N19/182 ,  H04N19/176

Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder comprises at least a fixed function dual hierarchical motion estimation search units, dual integer motion estimation search units, and a fractional motion estimation search unit. Moreover, the hardware bit packing unit is to pack bits as coded according to the final macroblock coding decision into a data format.

公开(公告)号：US20250117359A1

公开(公告)日：2025-04-10

申请号：US18913758

申请日：2024-10-11

Applicant: Intel Corporation

Inventor： Jorge Parra ,  Jiasheng Chen ,  Supratim Pal ,  Fangwen Fu ,  Sabareesh Ganapathy ,  Chandra Gurram ,  Chunhui Mei ,  Yue Qi

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.

公开(公告)号：US20250104180A1

公开(公告)日：2025-03-27

申请号：US18967172

申请日：2024-12-03

Applicant: Intel Corporation

Inventor： Abhishek Appu ,  Subramaniam Maiyuran ,  Mike Macpherson ,  Fangwen Fu ,  Jiasheng Chen ,  Varghese George ,  Vasanth Ranganathan ,  Ashutosh Garg ,  Joydeep Ray

IPC: G06T1/20 ,  G06F7/544 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0806 ,  G06F15/80 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084

Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

公开(公告)号：US20250036412A1

公开(公告)日：2025-01-30

申请号：US18358308

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Jiasheng Chen ,  Christopher Spencer ,  Jorge E. Parra Osorio ,  Kevin Hurd ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  Fangwen Fu ,  Wei Xiong ,  Hongzheng Li ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Shuai Mu ,  Clifford Gibson ,  Buqi Cheng

IPC: G06F9/30 ,  G06F9/38

Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a plurality of processing resources. A processing resource of the plurality of processing resources includes a source crossbar communicatively coupled with a register file, the source crossbar to reorder data elements of a source operand and a format conversion pipeline to convert a plurality of input data elements specified by the source operand from a first format of a plurality of datatype formats to a second format of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.

公开(公告)号：US20250036361A1

公开(公告)日：2025-01-30

申请号：US18358304

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Supratim Pal ,  Jiasheng Chen ,  Kevin Hurd ,  Jorge E. Parra Osorio ,  Christopher Spencer ,  Guei-Yuan Lueh ,  Pradeep K. Golconda ,  Fangwen Fu ,  Wei Xiong ,  Hongzheng Li ,  James Valerio ,  Mukundan Swaminathan ,  Nicholas Murphy ,  Shuai Mu ,  Clifford Gibson ,  Buqi Cheng

IPC: G06F7/483

Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format conversion pipeline including a plurality of parallel format conversion units configured to convert a plurality of input data elements from a first one of a plurality of datatype formats to a second one of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.

公开(公告)号：US11842423B2

公开(公告)日：2023-12-12

申请号：US17122905

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Abhishek Appu ,  Subramaniam Maiyuran ,  Mike Macpherson ,  Fangwen Fu ,  Jiasheng Chen ,  Varghese George ,  Vasanth Ranganathan ,  Ashutosh Garg ,  Joydeep Ray

IPC: G06F7/544 ,  G06F15/80 ,  G06F17/16 ,  G06T1/20 ,  G06F9/50 ,  G06F12/0806 ,  G06N3/084 ,  G06N3/08 ,  G06N3/048

CPC classification number: G06T1/20 ,  G06F7/5443 ,  G06F9/5027 ,  G06F12/0806 ,  G06F15/8046 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084

Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.

公开(公告)号：US11593454B2

公开(公告)日：2023-02-28

申请号：US16890122

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Fangwen Fu ,  Dhiraj D. Kalamkar ,  Sasikanth Avancha

IPC: G06F17/16 ,  G06F7/78 ,  G06N3/04 ,  G06N3/084

Abstract: An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.

公开(公告)号：US20220413803A1

公开(公告)日：2022-12-29

申请号：US17304803

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Jorge Parra ,  Fangwen Fu ,  Subramaniam Maiyuran ,  Varghese George ,  Mike Macpherson ,  Supratim Pal ,  Chandra Gurram ,  Sabareesh Ganapathy ,  Sasikanth Avancha ,  Dharma Teja Vooturi ,  Naveen Mellempudi ,  Dipankar Das

IPC: G06F7/544 ,  G06F7/523 ,  G06F15/80 ,  G06F17/16

Abstract: A processing apparatus is described herein that includes a general-purpose parallel processing engine comprising a matrix accelerator including one or more systolic arrays, at least one of the one or more systolic arrays comprising multiple pipeline stages, each pipeline stage of the multiple pipeline stages including multiple processing elements, the multiple processing elements configured to perform processing operations on input matrix elements based on output sparsity metadata. The output sparsity metadata indicates to the multiple processing elements to bypass multiplication for a first row of elements of a second matrix and multiply a second row of elements of the second matrix with a column of matrix elements of a first matrix.