公开(公告)号：US10020262B2

公开(公告)日：2018-07-10

申请号：US15199219

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sheng Li ,  Wei-Lun K. Jen

IPC: H01L23/538 ,  H01L21/027 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5384 ,  H01L21/0274 ,  H01L23/5381 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: In accordance with disclosed embodiments, there are provided high resolution solder resist material for silicon bridge application. For instance, in accordance with one embodiment, there is a silicon bridge disclosed, the silicon bridge having therein a solder resist layer formed from a high resolution solder resist material; in which the solder resist layer includes a polymer material which hardens when exposed to light radiation; in which the solder resist layer further includes spherical particles; a plurality of vias patterned into the solder resist layer by a photolithography process, the plurality of vias forming a set of larger vias and a set of smaller vias patterned into the solder resist layer by the photolithography process, each of the larger vias being greater in size than each of the smaller vias, and further in which each of the smaller vias are less than half the size of any one of the larger vias; in which the larger vias and the smaller vias provide through-silicon vias (TSVs) interconnects through the solder resist layer electrically interfacing two or more functional semiconductor devices affixed to the silicon bridge; and the silicon bridge further having therein a copper layer positioned below the solder resist layer. Other related embodiments are disclosed.

公开(公告)号：US20170301619A1

公开(公告)日：2017-10-19

申请号：US15641117

申请日：2017-07-03

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra J. Chavali ,  Robert A. May ,  Whitney M. Bryks

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31058 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/53228 ,  H01L23/53295

Abstract: Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

公开(公告)号：US20170179019A1

公开(公告)日：2017-06-22

申请号：US14972936

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra J. Chavali ,  Robert A. May ,  Whitney M. Bryks

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31058 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/53228 ,  H01L23/53295

Abstract: Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

公开(公告)号：US20230092492A1

公开(公告)日：2023-03-23

申请号：US17480064

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Xin Ning ,  Brandon C. Marin ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Numair Ahmed ,  Brent Williams ,  Mollie Stewart ,  Nathan Ou ,  Cary Kuliasha

IPC: H01L23/64 ,  H01F27/28 ,  H01L49/02 ,  H01L23/498 ,  H01L21/48

Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material. At least one third pathway extends through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.

公开(公告)号：US20220059367A1

公开(公告)日：2022-02-24

申请号：US17521406

申请日：2021-11-08

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US20210391232A1

公开(公告)日：2021-12-16

申请号：US17459993

申请日：2021-08-27

Applicant: INTEL CORPORATION

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US11195727B2

公开(公告)日：2021-12-07

申请号：US16901172

申请日：2020-06-15

Applicant: Intel Corporation

Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Schuckman

IPC: H01L21/48 ,  H01L23/498

Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.

公开(公告)号：US20210111088A1

公开(公告)日：2021-04-15

申请号：US16464547

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US10903137B2

公开(公告)日：2021-01-26

申请号：US16540177

申请日：2019-08-14

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra Jyotsna Chavali

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H01L23/367

Abstract: According to various embodiments of the present disclosure, an electrically conductive pillar having a substrate is disclosed. The electrically conductive pillar can comprise a first portion, second portion and a third portion. The first portion and/or third portion can be formed of an electrically conductive material that can be the same or different. The second portion can be intermediate and abut both the first portion and the third portion. The second portion can comprise a solder element formed of a second electrically conductive material that differs from the electrically conductive material and has a second stiffness less than a stiffness of the electrically conductive material.

公开(公告)号：US10384431B2

公开(公告)日：2019-08-20

申请号：US15475157

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ji Yong Park ,  Sri Chaitra J. Chavali ,  Siddharth K. Alur ,  Kyu Oh Lee

IPC: B32B37/10 ,  H05K3/46 ,  H05K3/00 ,  B32B37/06 ,  H05K3/02

Abstract: A method for forming a substrate structure for an electrical component includes placing an electrically insulating laminate on a substrate and applying hot pressure to the electrically insulating laminate by a heatable plate. An average temperature of a surface temperature distribution within a center area of the heatable plate is higher than 80° C. during applying the hot pressure. Further, an edge area of the heatable plate laterally surrounds the center area and a temperature of the heatable plate within the edge area decreases from the center area towards an edge of the heatable plate during applying the hot pressure. A temperature at a location located vertically above an edge of the substrate during applying the hot pressure is at least 5° C. lower than the average temperature of the surface temperature distribution within the center area.