公开(公告)号：NO20074706A

公开(公告)日：2007-11-13

申请号：NO20074706

申请日：2007-09-14

Applicant: INTERDIGITAL TECH CORP

Inventor： KAEWELL JR JOHN DAVID ,  REZNIK ALEXANDER ,  DIFAZIO ROBERT A ,  BECKER PETER EDWARD ,  LI BIN ,  PAN KYLE JUNG-LIN

IPC: H04B7/005

CPC classification number: H04L25/03159 ,  H04B17/336

公开(公告)号：NO20045635A

公开(公告)日：2005-02-16

申请号：NO20045635

申请日：2004-12-23

Applicant: INTERDIGITAL TECH CORP

Inventor： BECKER PETER EDWARD

IPC: G06F7/52

公开(公告)号：NO20044880L

公开(公告)日：2005-01-03

申请号：NO20044880

申请日：2004-11-09

Applicant: INTERDIGITAL TECH CORP

Inventor： SHAHRIER SHARIF M ,  BECKER PETER EDWARD ,  BUCHERT RYAN SAMUEL

IPC: G06F17/14

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.

公开(公告)号：NO20044880A

公开(公告)日：2005-01-03

申请号：NO20044880

申请日：2004-11-09

Applicant: INTERDIGITAL TECH CORP

Inventor： SHAHRIER SHARIF M ,  BECKER PETER EDWARD ,  BUCHERT RYAN SAMUEL

IPC: G06F17/14

CPC classification number: G06F17/144

Abstract: An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.