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    Data-mover controller with plural registers for supporting ciphering operations
    23.
    发明专利
    Data-mover controller with plural registers for supporting ciphering operations 未知

    公开(公告)号：AU2005332284A8

    公开(公告)日：2008-08-14

    申请号：AU2005332284

    申请日：2005-05-06

    Applicant: INTERDIGITAL TECH CORP

    Inventor： GAZDA ROBERT G ,  HEPLER EDWARD L

    IPC: H04L9/18 ,  G06F12/00 ,  G06F13/00 ,  G06F21/00 ,  H04L9/00 ,  H04L29/06

    Abstract: A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm “f8” or integrity cipher algorithm “f9”.

    25.
    发明专利
    未知

    公开(公告)号：NO20080490L

    公开(公告)日：2008-03-27

    申请号：NO20080490

    申请日：2008-01-25

    Applicant: INTERDIGITAL TECH CORP

    Inventor： REZNIK ALEXANDER ,  HEPLER EDWARD L ,  GAZDA ROBERT G

    IPC: H04J11/00 ,  H04L49/901 ,  H04W88/02

    Abstract: A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processes the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory.

    27.
    发明专利
    未知

    公开(公告)号：NO20065338L

    公开(公告)日：2007-01-19

    申请号：NO20065338

    申请日：2006-11-21

    Applicant: INTERDIGITAL TECH CORP

    Inventor： HEPLER EDWARD L ,  GAZDA ROBERT G

    IPC: G06F21/00 ,  H04L9/00 ,  H04L29/06

    Abstract: A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm “f8” or integrity cipher algorithm “f9”.

    System for generating pseudorandom sequences
    28.
    发明专利
    System for generating pseudorandom sequences 未知

    公开(公告)号：AU2002258723B2

    公开(公告)日：2005-05-12

    申请号：AU2002258723

    申请日：2002-04-05

    Applicant: INTERDIGITAL TECH CORP

    Inventor： HEPLER EDWARD L

    IPC: G06F1/025 ,  H03M7/00 ,  H04J11/00 ,  H04J13/00 ,  H04J13/12 ,  H04L20060101 ,  H04L9/00 ,  H04L27/30 ,  H04L027/30

    Abstract: A pseudorandom code generator comprising a code generator configured to generate a series of 2 M M-bit wide binary codes starting from a lowest bit to a highest bit; an index code selector configured to select an M-bit wide binary index code corresponding to an index number of a pseudorandom code among a set of pseudorandom codes; a logical operator configured to perform a logical operation between each code generated by the code generator and the index code selected by the index code selector in order to generate a 2 M -bit wide pseudorandom code; and a code reverser configured to reverse an order of bits generated by the code generator from a least significant bit to a most significant bit.

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