21.
    发明专利
    未知

    公开(公告)号:NO20065601L

    公开(公告)日:2007-01-31

    申请号:NO20065601

    申请日:2006-12-05

    Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.

    24.
    发明专利
    未知

    公开(公告)号:NO20044616L

    公开(公告)日:2004-10-26

    申请号:NO20044616

    申请日:2004-10-26

    Abstract: A wireless communication system implements wireless communications between a base station and a plurality of User Equipments (UEs) including paging of UEs by initially processing paging indicator information. A first embodiment involves a UE's physical layer L1 being configured for interpreting a paging indicator (PI) to activate a preset decoding configuration to process paging data in a pre-specified paging channel (PCH). A second embodiment involves the physical layer control of a next higher level, L2, interpreting the paging indicator and configuring the physical layer L1 to process paging data in a pre-specified PCH.

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