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公开(公告)号:NO20065601L
公开(公告)日:2007-01-31
申请号:NO20065601
申请日:2006-12-05
Applicant: INTERDIGITAL TECH CORP
Inventor: CASTOR DOUGLAS R , LEVI ALAN M , DESAI BINISH P
Abstract: A method and apparatus for efficiently allocating and deallocating interleaved data stored in a memory stack. The apparatus includes a processor and a memory including at least one memory stack. The processor receives and interleaves a plurality of data blocks. Each data block is allocated for a particular transport channel (TrCH) and has a designated transmission timing interval (TTI). The processor stores the interleaved data blocks in the memory stack based on the TTI of each data block, such that a data block having a larger TTI is allocated to the memory stack earlier and deallocated from the stack later than a data block having a smaller TTI. In one embodiment, the memory includes a first memory stack for common/shared uplink channels, a second memory stack for dedicated uplink channels, a third memory stack for common/shared downlink channels, and a fourth memory stack for dedicated downlink channels.
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公开(公告)号:AT350822T
公开(公告)日:2007-01-15
申请号:AT03719734
申请日:2003-04-15
Applicant: INTERDIGITAL TECH CORP
Inventor: HEPLER EDWARD L , STARSINIC MICHAEL F , BASS DAVID S , DESAI BINISH , LEVI ALAN M , MCCLELLAN GEORGE W , CASTOR DOUGLAS R
IPC: H04J1/00 , H04B1/40 , H04B1/707 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02
Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
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公开(公告)号:NO20044923L
公开(公告)日:2005-01-05
申请号:NO20044923
申请日:2004-11-11
Applicant: INTERDIGITAL TECH CORP
Inventor: HEPLER EDWARD L , CASTOR DOUGLAS R , MCCLELLAN GEORGE W , STARSINIC MICHAEL F , LEVI ALAN M , BASS DAVID S , DESAI BINISH
IPC: H04B1/40 , H04B1/707 , H04J1/00 , H04B7/26 , H04J3/00 , H04J4/00 , H04L1/00 , H04L1/08 , H04L12/56 , H04W28/18 , H04W74/02 , H04W80/00 , H04W88/02 , G06F13/00
Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block (305,307), a composite channel processing block (303,309) and a chip rate processing block (301,311). At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.
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公开(公告)号:NO20044616L
公开(公告)日:2004-10-26
申请号:NO20044616
申请日:2004-10-26
Applicant: INTERDIGITAL TECH CORP
Inventor: MCCLELLAN GEORGE W , KEARNEY KENNETH P , DRUMMOND RYAN ERIC , LEVI ALAN M
Abstract: A wireless communication system implements wireless communications between a base station and a plurality of User Equipments (UEs) including paging of UEs by initially processing paging indicator information. A first embodiment involves a UE's physical layer L1 being configured for interpreting a paging indicator (PI) to activate a preset decoding configuration to process paging data in a pre-specified paging channel (PCH). A second embodiment involves the physical layer control of a next higher level, L2, interpreting the paging indicator and configuring the physical layer L1 to process paging data in a pre-specified PCH.
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