公开(公告)号：US10692921B2

公开(公告)日：2020-06-23

申请号：US16566171

申请日：2019-09-10

Applicant: Infineon Technologies AG

Inventor： Dirk Meinhold ,  Emanuele Bruno Bodini ,  Felix Braun ,  Hermann Gruber ,  Uwe Hoeckele ,  Dirk Offenberg ,  Klemens Pruegl ,  Ines Uhlig

IPC: H01L27/146 ,  H01L27/148

Abstract: Techniques are discloses regarding methods of manufacturing an imager as well as an imager device.

公开(公告)号：US10411060B2

公开(公告)日：2019-09-10

申请号：US15586498

申请日：2017-05-04

Applicant: Infineon Technologies AG

Inventor： Dirk Meinhold ,  Emanuele Bruno Bodini ,  Felix Braun ,  Hermann Gruber ,  Uwe Hoeckele ,  Dirk Offenberg ,  Klemens Pruegl ,  Ines Uhlig

IPC: H01L27/146 ,  H01L27/148

Abstract: Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.

公开(公告)号：US20170194417A1

公开(公告)日：2017-07-06

申请号：US15465715

申请日：2017-03-22

Applicant: Infineon Technologies AG

Inventor： Hermann Gruber ,  Thomas Gross ,  Werner Irlbacher ,  Markus Zundel ,  Mathias von Borcke ,  Hans Joachim Schulze

IPC: H01L49/02 ,  H01L21/266

CPC classification number: H01L28/20 ,  G01K7/186 ,  H01L21/266 ,  H01L27/0802

Abstract: A method for producing a polysilicon resistor device may include: forming a polysilicon layer; implanting first dopant atoms into at least a portion of the polysilicon layer, wherein the first dopant atoms include deep energy level donors; implanting second dopant atoms into said at least a portion of said polysilicon layer; and annealing said at least a portion of said polysilicon layer.

公开(公告)号：US20160380063A1

公开(公告)日：2016-12-29

申请号：US15189147

申请日：2016-06-22

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Anton Mauder ,  Hermann Gruber ,  Hubert Rothleitner ,  Andreas Peter Meiser

IPC: H01L29/40

CPC classification number: H01L29/407 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823481 ,  H01L23/481 ,  H01L24/16 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/16245 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer.

Abstract translation: 提供一种半导体元件的制造方法。 该方法包括：提供具有与第一表面相对的第一表面和第二表面的半导体本体，将绝缘沟槽从第一表面部分地蚀刻到半导体本体中，在绝缘沟槽的一个或多个侧壁上形成第一绝缘层， 通过研磨，抛光和CMP工艺中的至少一个来处理第二表面以暴露第一绝缘层，以及在经处理的第二表面上沉积延伸到第一绝缘层的第二绝缘层。

公开(公告)号：US09275895B2

公开(公告)日：2016-03-01

申请号：US14166090

申请日：2014-01-28

Applicant: Infineon Technologies AG

Inventor： Andreas Meiser ,  Walter Hartner ,  Hermann Gruber ,  Dietrich Bonart ,  Thomas Gross

IPC: H01L21/763 ,  H01L21/768 ,  H01L21/762 ,  H01L27/105 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/76802 ,  H01L21/76286 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/1203

Abstract: A method for producing a semiconductor component with a semiconductor body includes providing a substrate of a first conductivity type. A buried semiconductor layer of a second conductivity type is provided on the substrate. A functional unit semiconductor layer is provided on the buried semiconductor layer. At least one trench, which reaches into the substrate, is formed in the semiconductor body. An insulating layer is formed, which covers inner walls of the trench and electrically insulates the trench interior from the functional unit semiconductor layer and the buried semiconductor layer, the insulating layer having at least one opening in the region of the trench bottom. The at least one trench is filled with an electrically conductive semiconductor material of the first conductivity type, wherein the electrically conductive semiconductor material forms an electrical contact from a surface of the semiconductor body to the substrate.

Abstract translation: 一种制造具有半导体本体的半导体部件的方法，包括提供第一导电型的基板。 在基板上设置第二导电类型的掩埋半导体层。 功能单元半导体层设置在掩埋半导体层上。 至少一个到达衬底的沟槽形成在半导体本体中。 形成绝缘层，其覆盖沟槽的内壁，并使沟槽内部与功能单元半导体层和埋入半导体层电绝缘，绝缘层在沟槽底部的区域中具有至少一个开口。 所述至少一个沟槽填充有第一导电类型的导电半导体材料，其中所述导电半导体材料形成从所述半导体主体的表面到所述衬底的电接触。

公开(公告)号：US20140299972A1

公开(公告)日：2014-10-09

申请号：US14249642

申请日：2014-04-10

Applicant: Infineon Technologies AG

Inventor： Hermann Gruber ,  Thomas Gross ,  Andreas Peter Meiser ,  Markus Zundel

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/6835 ,  H01L21/76224 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate having a first side and a second side opposite the first side, an active area and a through contact area, the active area including a transistor structure having a control electrode, the through contact area including a semiconductor mesa having insulated sidewalls. The semiconductor device further includes a first metallization on the first side in the active area and a recess extending from the first side into the semiconductor substrate and between the active area and the through contact area and including in the through contact area a horizontally widening portion, the recess being at least partly filled with a conductive material forming a first conductive region in ohmic contact with the semiconductor mesa and the transistor structure. The semiconductor device also includes a control metallization on the second side and in ohmic contact with the semiconductor mesa.

Abstract translation: 半导体器件包括具有第一侧和与第一侧相对的第二侧的半导体衬底，有源区和贯通接触区，所述有源区包括具有控制电极的晶体管结构，所述贯通接触区包括半导体台面，所述半导体衬底具有 绝缘侧壁。 所述半导体器件还包括在所述有源区域中的第一侧上的第一金属化和从所述第一侧延伸到所述半导体衬底中以及在所述有源区域和所述贯穿接触区域之间并且在所述贯穿接触区域中包括水平扩大部分的凹部， 所述凹部至少部分地填充有形成与所述半导体台面和所述晶体管结构欧姆接触的第一导电区域的导电材料。 半导体器件还包括在第二侧上的控制金属化并与半导体台面欧姆接触。

公开(公告)号：US20140070232A1

公开(公告)日：2014-03-13

申请号：US13776796

申请日：2013-02-26

Applicant: Infineon Technologies AG

Inventor： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L29/16

CPC classification number: H01L21/76251 ,  H01L21/02002 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02527 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/7624 ,  H01L29/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161

Abstract: A composite wafer including a carrier substrate having a graphite core and a monocrystalline semiconductor substrate or layer attached to the carrier substrate and a corresponding method for manufacturing such a composite wafer is provided.

Abstract translation: 提供了一种复合晶片，其包括具有石墨芯和附着于载体基板的单晶半导体衬底或层的载体衬底和用于制造这种复合晶片的相应方法。