公开(公告)号：US11749560B2

公开(公告)日：2023-09-05

申请号：US16141522

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Thomas Marieb ,  Zhiyong Ma ,  Miriam R. Reshotko ,  Christopher Jezewski ,  Flavio Griggio ,  Rahim Kasim ,  Nikholas G. Toledo

IPC: H01L21/768 ,  H01L23/532 ,  C25D3/58 ,  C23C18/48

CPC classification number: H01L21/76802 ,  C23C18/48 ,  C25D3/58 ,  H01L21/76849 ,  H01L21/76852 ,  H01L23/53223 ,  H01L23/53238

Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.

公开(公告)号：US20230197601A1

公开(公告)日：2023-06-22

申请号：US17558423

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jiun-Ruey Chen ,  Christopher Jezewski ,  John Plombon ,  Miriam Reshotko ,  Mauro Kobrinsky ,  Scott B. Clendenning

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/5328 ,  H01L23/53238 ,  H01L21/76879 ,  H01L21/76807

Abstract: Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.

公开(公告)号：US20220415818A1

公开(公告)日：2022-12-29

申请号：US17358962

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Jasmeet Chawla ,  Matthew Metz ,  Sean King ,  Ramanan Chebiam ,  Mauro Kobrinsky ,  Scott Clendenning ,  Sudarat Lee ,  Christopher Jezewski ,  Sunny Chugh ,  Jeffery Bielefeld

IPC: H01L23/532 ,  H01L21/3215 ,  H01L21/768

Abstract: Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

公开(公告)号：US20220352068A1

公开(公告)日：2022-11-03

申请号：US17841551

申请日：2022-06-15

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11444024B2

公开(公告)日：2022-09-13

申请号：US17087519

申请日：2020-11-02

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/768

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US11276644B2

公开(公告)日：2022-03-15

申请号：US16221798

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L23/532 ,  H01L29/45 ,  H01L29/786 ,  H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L21/285

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

公开(公告)号：US11171239B2

公开(公告)日：2021-11-09

申请号：US16570965

申请日：2019-09-13

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US20210083122A1

公开(公告)日：2021-03-18

申请号：US16570965

申请日：2019-09-13

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US20160242279A1

公开(公告)日：2016-08-18

申请号：US15012557

申请日：2016-02-01

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H05K1/03 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K3/28

CPC classification number: H05K1/038 ,  D03D1/0088 ,  D03D11/02 ,  D03D15/00 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/10 ,  H05K3/28 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/029

Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

公开(公告)号：US12211794B2

公开(公告)日：2025-01-28

申请号：US17648821

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Anil Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H01L21/285

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.