公开(公告)号：US10779405B2

公开(公告)日：2020-09-15

申请号：US16045236

申请日：2018-07-25

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/18 ,  H05K3/42 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

Abstract: A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.

公开(公告)号：US10440837B2

公开(公告)日：2019-10-08

申请号：US15864754

申请日：2018-01-08

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H01K3/10 ,  H05K3/42 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

Abstract: A manufacturing method of a double layer circuit board comprises forming at least one connecting pillar on a first circuit, wherein the at least one connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the at least one connecting pillar; drilling the substrate to expose a portion of the second end of the at least one connecting pillar, wherein the other portion of the second end of the at least one connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the at least one connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

公开(公告)号：US10383265B2

公开(公告)日：2019-08-13

申请号：US16115119

申请日：2018-08-28

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. The EMI shielding device is adopted to be mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.

公开(公告)号：US20180303012A1

公开(公告)日：2018-10-18

申请号：US15859982

申请日：2018-01-02

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yung-Lin Chia

IPC: H05K9/00

Abstract: An EMI shielding device is provided. A first shielding layer is formed on a first surface of a first substrate, and a first through hole is formed through the first substrate. A second substrate is mounted in an opening of the first through hole, and a second shielding layer is formed on a surface of the second substrate. A conductive paste is mounted between the first substrate and the at least one second substrate to electrically connected the first shielding layer and the second shielding layer. The EMI shielding device is adopted to be mounted on a printed circuit board (PCB) by Surface Mount Technology. Therefore, the EMI shielding device may be firmly mounted on the PCB, and there is not any narrow gap that may leak electromagnetic radiation.

公开(公告)号：US09831167B1

公开(公告)日：2017-11-28

申请号：US15678130

申请日：2017-08-16

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Kuo-Chun Huang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/13 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/061 ,  H01L2924/00

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with an opening bonded to a carrier board in order to form a compound carrier board structure. A die is placed in the opening and bonded to the carrier board. A sealant is filled in a gap between surrounding walls of the opening and the die at a height lower than the die to fixedly place the die within the opening and to leave a non-active surface of the die exposed.

公开(公告)号：US20170299632A1

公开(公告)日：2017-10-19

申请号：US15130982

申请日：2016-04-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: G01R1/073 ,  G01R31/28

CPC classification number: G01R1/07378 ,  G01R1/07328 ,  G01R31/2808

Abstract: A printed circuit board (PCB) test fixture includes a substrate, a first insulation layer formed on the substrate, a conductor layer formed on the first insulation layer and electrically connected to the upper electrodes through at least one first connection member, a second insulation layer formed on the first insulation layer, and multiple conductive cones arranged on the second insulation layer in a matrix form. A part of the conductive cones is electrically connected to the conductor layer through at least one second connection member. The circuit layout of the conductor layer, the at least one first connection member and the at least one second connection member is employed to supply testing power to a part of the conductive cones and an adjustable arrangement of the conductive cones to enhance density of test probes upon electrical testing.

公开(公告)号：US09754870B2

公开(公告)日：2017-09-05

申请号：US15071368

申请日：2016-03-16

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Shuo-Hsun Chang ,  Yu-Te Lu ,  Kuo-Chun Huang

IPC: H01L23/498 ,  H01L23/31 ,  H05K3/46 ,  H01L23/00 ,  H01L25/10 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/15787 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/4697 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/061 ,  H01L2924/00

Abstract: A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with a penetrating rectangular opening bonded to a non-conductive film then a carrier board in order to form a compound carrier board structure. The baseplate is constructed with a low Thermal Expansion Coefficient material.

公开(公告)号：US20160262269A1

公开(公告)日：2016-09-08

申请号：US14640993

申请日：2015-03-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K3/18 ,  H05K3/06

CPC classification number: H05K3/205 ,  H05K2201/0376 ,  H05K2203/0376

Abstract: Disclosed is a copper etching method for manufacturing a circuit board, including steps of electroplating a metal copper support layer, coating a thermal sensitive photo resist layer, coating a photo resist layer, performing a process of pattern transfer, removing part of the photo resist layer to form a photo resist pattern, electroplating a metal copper layer to form a circuit pattern, peeling off the photo resist layer, pressing a stacked body composed of a stacked substrate and a stacked material layer onto the circuit pattern to embed the circuit pattern in the stacked material layer, removing the base layer, performing a copper etching process to removing the metal copper support layer, and removing the thermal sensitive photo resist layer to expose the circuit pattern. In particular, the circuit pattern protrudes from the stacked material layer so as to facilitate the subsequent process of forming solder balls.

Abstract translation: 公开了一种用于制造电路板的铜蚀刻方法，包括以下步骤：电镀金属铜支撑层，涂覆热敏光致抗蚀剂层，涂覆光致抗蚀剂层，执行图案转印工艺，去除部分光致抗蚀剂层 以形成光刻胶图形，电镀金属铜层以形成电路图案，剥离光致抗蚀剂层，将由堆叠的基板和堆叠的材料层组成的堆叠体压在电路图案上，以将电路图案嵌入到 层叠材料层，去除基底层，进行铜蚀刻工艺以除去金属铜载体层，以及去除热敏光刻胶层以暴露电路图案。 特别地，电路图案从堆叠的材料层突出，以便于随后的形成焊球的工艺。

公开(公告)号：US20150282306A1

公开(公告)日：2015-10-01

申请号：US14225671

申请日：2014-03-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K3/4679 ,  H05K1/116 ,  H05K2201/0376

Abstract: A multilayer substrate structure includes a first plastic sheet, a second plastic sheet, a first circuit pattern layer, a second circuit pattern layer, and an interlayer connection pad. A first connection plug connected to the interlayer connection pad fills in a first opening of a first plastic sheet and is connected to a first connection pad of the first circuit pattern layer. A second connection plug fills a second opening of the second plastic sheet and is connected to a second connection pad of the second circuit pattern layer such that the second circuit pattern layer is electrically connected to the first circuit pattern layer via the interlayer connection pad. Therefore, even if there is little offset, it is possible to overcome the alignment tolerance and assure electrical connection between the circuit layers as desired.

Abstract translation: 多层基板结构包括第一塑料片，第二塑料片，第一电路图案层，第二电路图案层和层间连接垫。 连接到层间连接焊盘的第一连接插头填充第一塑料片的第一开口并连接到第一电路图案层的第一连接焊盘。 第二连接插头填充第二塑料片的第二开口并且连接到第二电路图案层的第二连接焊盘，使得第二电路图案层经由层间连接焊盘电连接到第一电路图案层。 因此，即使几乎没有偏移，也可以克服对准公差，并且根据需要确保电路层之间的电连接。

公开(公告)号：US08941224B2

公开(公告)日：2015-01-27

申请号：US13853281

申请日：2013-03-29

Applicant: Kinsus Interconnect Technology Corp.

Inventor： Ting-Hao Lin ,  Yu-Te Lu ,  De-Hao Lu

IPC: H01L23/06 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/563 ,  H01L23/49861 ,  H01L23/49894 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion.

Abstract translation: 封装结构包括薄片基板，稳定材料层，芯片和填充材料。 衬底的第一电路金属层嵌入电介质层中，并且由第一电路金属层和电介质层限定共面，并从电介质层露出。 衬底的接合焊盘在共面上，具有高于共面的高度并连接到第一电路金属层。 稳定材料层设置在共面的两侧，以限定用于容纳芯片的容纳空间。 将填充材料注入到接收空间中，用粘合垫牢固地固定芯片的销。 由于不需要塑料成型，所以包装结构的总厚度和成本降低。 稳定材料层防止基材翘曲和变形。