公开(公告)号：GB2312095B

公开(公告)日：1997-12-17

申请号：GB9710128

申请日：1994-12-14

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO KEOK-HO ,  KANG JIN-YOUNG

IPC: H01L21/762 ,  H01L21/3105

公开(公告)号：DE19650493A1

公开(公告)日：1997-06-26

申请号：DE19650493

申请日：1996-12-05

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  CHO DEOK-HO ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  PYUN KWANG-EUI

IPC: H01L21/331 ,  H01L29/737 ,  H01L29/73 ,  H01L21/76

Abstract: The transistor includes a semiconductor substrate, e.g. of silicon, with a buried collector and having an oxide film with a conductive, thin-film base electrode formed on the substrate one after another. The substrate is provided with a heterojunction of e.g. Si or SiGe Ge. The collector is surrounded by the conductive thin film and is formed in transistor active region, bounded by patterns of the conductive thin and first oxide films on the buried collector on both sides of the conductive thin film is formed a first spacing layer. A multilayer base is formed in the active region, while an emitter is grown selectively on the base in an emitter region, bounded by etching of a second oxide film, on whose both sides is formed a second spacing layer. The emitter carries an electrode, while a passivating insulation layer is formed on the structure surface. Metal coupling lines are formed on the base, emitter, and buried collector and go back through the insulation passivation layer and/or the two oxide layers.

公开(公告)号：DE4444776A1

公开(公告)日：1996-06-27

申请号：DE4444776

申请日：1994-12-15

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  CHO DEOK-HO ,  LEE SEONG-HEARN ,  KANG JIN-YOUNG

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/737 ,  H01L29/735

Abstract: Disclosed is a fabrication of a bipolar transistor with a super self-aligned vertical structure in which emitter, base and collector are vertically self-aligned, the fabrication method comprising the steps of forming a conductive buried collector region in a silicon substrate by using ion-implantation of an impurity and thermal-annealing; sequentially forming several layers; selectively removing the nitride and polysilicon layers to form a pattern; sequentially forming a silicon oxide layer, a third layer and a silicon oxide layer thereon; forming a patterned photoresist layer thereon to define active and inactive regions and removing several layers on the active region to form an opening; forming a side wall on both sides of the opening; forming a collector on a surface portion of the buried collector region up to a lower surface of the polysilicon layer; removing the side wall and the third nitride layer to expose a side surface of the second polysilicon layer; selectively forming a base on an upper surface of the collector including a side surface of the polysilicon layer; forming side wall oxide layer on both sides of the base and the silicon oxide to define an emitter region; forming an emitter on the base; and forming electrodes thereon. In the method, an active region is defined by a photolithography, and thereby a trench isolation acting as factors of lowering in integration and device-performance can be omitted in the method. As a result, fabrication sequence can be simplified and integration can be improved.

公开(公告)号：GB2296375A

公开(公告)日：1996-06-26

申请号：GB9425590

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM ,  KOREA TELECOMMUNICATION

Inventor： RYUM BYUNG-RYUL ,  CHO DEOK-HO ,  HAN TAE-HYEON ,  LEE SOO-MIN ,  KWON OH-JOON

IPC: H01L21/331 ,  H01L29/737

Abstract: Disclosed is a fabrication of a hetero-junction bipolar transistor in which a base parasitic capacitance is reduced by using a metallic silicide as the base (25), comprising the steps of injecting an impurity in a silicon substrate to form a conductive buried collector region (21); growing a collector epitaxial layer (22) on the buried collector region and forming a field oxide layer (23); selectively injecting an impurity into the collector epitaxial layer to form a collector sinker; sequentially forming a base layer (25) and a first oxide layer thereon; patterning the first oxide layer to define an extrinsic base region; ion-implanting an impurity in the extrinsic base region using a patterned oxide layer as a mask and removing the patterned oxide layer; depositing a metallic silicide film (26) thereon to form a base electrode thin film; forming a capping oxide layer (27), forming an isolating oxide layer thereon and sequentially and selectively removing the isolating oxide layer, the capping oxide layer, the base electrode thin film and the base layer using a patterned photomask, removing a portion of the isolating oxide layer to define an emitter region; forming a passivation layer thereon and selectively removing the passivation layer to form contact holes; and depositing a polysilicon layer doped with impurity ions in the contact holes to form electrodes.