公开(公告)号：WO1995028737A1

公开(公告)日：1995-10-26

申请号：PCT/US1995004690

申请日：1995-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  FARNWORTH, Warren, M. ,  FOLARON, Jennifer, L. ,  FOLARON, Robert, J. ,  HEMBREE, David, R. ,  JACOBSON, John, O. ,  NELSON, Jay, C. ,  WARREN, Lelan, D.

IPC: H01L21/00

CPC classification number: H01L21/67276 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2893 ,  G01R31/311 ,  H01L21/67126 ,  H01L21/67242 ,  H01L21/67259 ,  H01L21/681 ,  H01L24/74 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K13/08 ,  Y10T29/49004 ,  Y10T29/49131 ,  Y10T29/53174 ,  Y10T29/53178 ,  H01L2924/00

Abstract: An apparatus for automatically positioning electronic die within temporary packages to enable continuity testing and the like between the die bond pads and the temporary package electrical interconnects is provided. The apparatus includes a robot having a programmable robot arm with a gripper assembly, die and lid feeder stations, a die inverter, and a plurality of cameras or image producers. The cameras take several pictures of the die and temporary packages to precisely align the die bond pads with the temporary package electrical interconnects. A predetermined assembly position is located along a conveyor that conveys a carrier between a first position, corresponding to an inlet, and a second position, corresponding to an outlet. The die, a restraining device and temporary package are assembled at the predetermined assembly position and tested for continuity therebetween. The apparatus further includes a fifth camera which locates the die at a wafer handler. The apparatus has a control mechanism including a microprocessor and associated program routines that selectively control the robot arm (i) to move the gripper assembly to the lid feeder station to pick up a lid, (ii) to move the gripper assembly along with the lid to pick up the die following photographing by the rough die camera, (iii) to move the gripper assembly along with the lid and the die to a position to be photographed by the fine die camera, and (iv) to move the lid and the die to the predetermined assembly position located along the conveyor. The method and apparatus may also be used for disassembly.

Abstract translation: 提供一种用于将电子管芯自动定位在临时封装内以使得管芯接合焊盘和临时封装电互连之间的连续性测试等的装置。 该装置包括具有可编程机器人臂的机器人，该机器人臂具有夹持器组件，模具和盖子馈送站，模具逆变器以及多个相机或图像生成器。 相机拍摄模具和临时包装的几张照片，以便将芯片接合焊盘与临时封装电气互连精确对准。 预定的组装位置沿着输送机定位，该输送器在对应于出口的第一位置（对应于入口）和第二位置之间输送载体。 模具，约束装置和临时包装组装在预定的组装位置，并测试其间的连续性。 该设备还包括一个将晶片定位在晶片处理器上的第五相机。 该装置具有包括微处理器和相关程序例程的控制机构，其选择性地控制机器人手臂（i）将夹持器组件移动到盖子馈送站以拾起盖子，（ii）沿着盖子移动夹持器组件 通过粗模相机拍摄后拾取模具，（iii）将夹具组合件与盖和模具一起移动到由精细模具相机拍摄的位置，以及（iv）移动盖子和 沿着输送机到达预定的组装位置。 该方法和装置也可以用于拆卸。

公开(公告)号：WO1991013392A2

公开(公告)日：1991-09-05

申请号：PCT/US1991000987

申请日：1991-02-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HESSON, James

IPC: G06F07/50

CPC classification number: G06F7/501 ,  G06F2207/3876 ,  H03K19/09429 ,  H03K19/1736

Abstract: Fast CMOS fully differential logic circuitry, using only tristatable buffers, and capable of as low as a single transistor propagation delay. The preferred embodiment of the invention includes four tristatable buffers (A1, A2, A3, and A4) connected together in such a way as to have multiple differential inputs and one differential output. Different configurations of the output and inputs make different logic functions available. An alternate embodiment combines three of these logic circuits to make a fully differential 3-input full adder, generating sum (SUM/SUM*) and carry outputs (COUT/COUT*) within two transistor delays.

Abstract translation: 快速CMOS全差分逻辑电路，仅使用可调缓冲器，并且能够低至单个晶体管传播延迟。 本发明的优选实施例包括以能够具有多个差分输入和一个差分输出的方式连接在一起的四个可跟踪缓冲器（A1，A2，A3和A4）。 输出和输入的不同配置使不同的逻辑功能可用。 一个替代实施例组合了这三个逻辑电路以产生全差分3输入全加器，产生和（SUM / SUM *）并且在两个晶体管延迟之内传送输出（COUT / COUT *）。

公开(公告)号：WO1998022635A1

公开(公告)日：1998-05-28

申请号：PCT/US1997020731

申请日：1997-11-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SHARAN, Sujit ,  SANDHU, Gurtej, S.

IPC: C23C14/28

CPC classification number: H01L21/2855 ,  C23C14/046 ,  C23C14/28 ,  H01L21/76877 ,  H01L21/76898

Abstract: A method and apparatus for laser ablation deposition of materials onto a substrate (30). The disclosed method and apparatus facilitate the deposition of thin films of a target material (24) onto a substrate (30) having features of high aspect ratio, e.g., an aspect ratio greater than one. In one embodiment, a laser ablation apparatus is provided in which the target support and substrate (wafer) support are independently angularly adjustable (54, 56), such that the angle ( theta A) at which material ablated from the target (24) is deposited onto the substrate (30) can be adjusted and controlled. Uniformity of deposited layers may be further enhanced by moving (e.g., rotating or raster scanning) the target (24) with respect to the laser and/or by moving (e.g., rotating or raster scanning) the substrate (30) with respect to the target (24).

Abstract translation: 一种用于将材料激光烧蚀沉积到衬底（30）上的方法和装置。 所公开的方法和装置有助于将目标材料（24）的薄膜沉积到具有高纵横比（例如，大于1的纵横比）的特征的基底（30）上。 在一个实施例中，提供了一种激光烧蚀装置，其中目标支撑件和衬底（晶片）支撑件是独立的可角度调整的（54,56），使得从靶材（24）消除的材料的角度（θA） 可以调节和控制沉积在基底（30）上的沉积物。 可以通过相对于激光器移动（例如，旋转或光栅扫描）目标（24）和/或通过相对于激光器移动（例如，旋转或光栅扫描）基板（30）来进一步增强沉积层的均匀性 目标（24）。

公开(公告)号：WO1998019330A1

公开(公告)日：1998-05-07

申请号：PCT/US1997019775

申请日：1997-10-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  PAN, Pai-Hung

IPC: H01L21/28

CPC classification number: H01L21/28061 ,  H01L29/4941

Abstract: Methods and apparatus for forming word line stacks are comprised of a silicon diffusion barrier region, doped with oxygen or nitrogen, coupled between a bottom silicon layer and a conductor layer. Word line stacks formed by the methods of the invention are used in sub-0.25 micron line width applications and have a lower resistivity and improved thermal stability.

Abstract translation: 用于形成字线堆叠的方法和装置由掺杂有氧或氮的硅扩散阻挡区域组成，耦合在底部硅层和导体层之间。 通过本发明的方法形成的字线叠层用于0.25μm以下的线宽应用中，具有较低的电阻率和改善的热稳定性。

公开(公告)号：WO1998015384A1

公开(公告)日：1998-04-16

申请号：PCT/US1997017799

申请日：1997-10-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  HENDERSON, Gary, O.

IPC: B24B37/04

CPC classification number: B24B37/20 ,  B24B37/26

Abstract: A contour indicator that visually indicates non-uniformities in the planarity of the planarizing surface of a polishing pad. In one embodiment of the invention, a polishing pad has a polishing body with a planarizing surface facing the wafer and a contour indicator embedded in the polishing body. The contour indicator is preferably the material of the polishing body dyed to a color or shade that is visually distinguishable from the polishing body. The contour indicator preferably has first and second sidewalls spaced apart from one another at the planarizing surface of the polishing body, and the contour indicator also has a cross-sectional shape so that the distance between the first and second sidewalls changes with increasing the depth within the pad. In operation, the distance between the first and second sidewalls of the contour indicator changes as material is removed from the planarizing surface, and the distance between the first and second sidewalls at the planarizing surface indicates the contour of the planarizing surface.

Abstract translation: 轮廓指示器，其可视地表示抛光垫的平坦化表面的平坦度的不均匀性。 在本发明的一个实施例中，抛光垫具有抛光体，其具有面向晶片的平坦化表面和嵌入抛光体​​中的轮廓指示器。 轮廓指示器优选地是被抛光到颜色或阴影的抛光体的材料，其在视觉上可与抛光体相区别。 轮廓指示器优选地具有在抛光体的平坦化表面处彼此间隔开的第一和第二侧壁，并且轮廓指示器还具有横截面形状，使得第一和第二侧壁之间的距离随着内部深度的增加而变化 垫 在操作中，轮廓指示器的第一和第二侧壁之间的距离随着材料从平坦化表面移除而变化，平坦化表面处的第一和第二侧壁之间的距离表示平坦化表面的轮廓。

公开(公告)号：WO1998006103A1

公开(公告)日：1998-02-12

申请号：PCT/US1997013775

申请日：1997-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  BEFFA, Ray

IPC: G11C29/00

CPC classification number: G11C29/08 ,  G01R31/318371 ,  G01R31/319 ,  G06F11/006 ,  G11C29/10 ,  G11C29/26 ,  G11C29/44

Abstract: A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

Abstract translation: 一种用于测试诸如DRAM的半导体存储器芯片的方法和装置，其具有多个存储单元或位。 每个存储器芯片具有存储在数据库中的唯一标识符。 对存储器芯片进行测试，并且当存储器芯片未通过测试时，将存储器芯片放置在修理槽中，并且与存储器芯片标识符相关联地将测试标识符存储在数据库中。 为了修复存储器芯片，从数据库中读出失败的测试，并且在故障存储器芯片上再次执行这样的测试，以便确定存储器芯片中的哪个存储器单元是有故障的。 然后修复失败的内存单元。

公开(公告)号：WO1997028532A1

公开(公告)日：1997-08-07

申请号：PCT/US1997001569

申请日：1997-01-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

IPC: G11C11/409

CPC classification number: G11C7/18 ,  G11C11/4097

Abstract: A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6F or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.

Abstract translation: 描述了一种新颖的双层DRAM架构，其在保持传统折叠架构的噪声性能的同时实现了裸片尺寸的显着降低。 芯片尺寸的减小主要是通过以一种交叉点存储单元布局构建具有6F 2或更小的存储单元的存储器阵列。 存储器阵列利用堆叠数字线和垂直数字线扭转来实现折叠架构操作和噪声性能。

公开(公告)号：WO1997026679A1

公开(公告)日：1997-07-24

申请号：PCT/US1997000757

申请日：1997-01-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  McTEER, Everett, A. ,  ZAHORIK, Russell, C. ,  MEIKLE, Scott, G.

IPC: H01L31/0232

CPC classification number: H01L21/76849 ,  H01J1/52 ,  H01J29/896 ,  H01J31/127 ,  H01J2201/30403 ,  H01J2201/319 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/7685 ,  H01L21/76858 ,  H01L21/76885 ,  H01L23/53223 ,  H01L31/02161 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Titanium aluminum nitrogen ("Ti-Al-N") is deposited onto a semiconductor substrate area to serve as an antireflective coating. For wiring line fabrication processes, the Ti-Al-N layer serves as a cap layer (56) which prevents unwanted reflection of photolithography light (i.e., photons) during fabrication. For field emission display devices (FEDs) (150), the Ti-Al-N layer (200) prevents light originating at the display screen (118) anode from penetrating transistor junctions that would hinder device operation. For the wiring line embodiment an aluminum conductive layer (54) and a titanium-aluminum underlayer (52) are formed beneath the antireflective cap layer. The Ti-Al underlayer reduces the shrinkage which occurs in the aluminum conductive layer during heat treatment.

Abstract translation: 将钛铝氮（“Ti-Al-N”）沉积到半导体衬底区域上以用作抗反射涂层。 对于布线制造工艺，Ti-Al-N层用作覆盖层（56），其防止在制造期间光刻光（即光子）的不期望的反射。 对于场发射显示装置（FED）（150），Ti-Al-N层（200）防止源自显示屏（118）阳极的光穿透将阻碍器件操作的晶体管结。 对于布线实施例，铝合金导电层（54）和钛 - 铝底层（52）形成在防反射盖层下面。 Ti-Al底层减少了在热处理期间在铝导电层中发生的收缩。

公开(公告)号：WO1997025674A1

公开(公告)日：1997-07-17

申请号：PCT/US1996020113

申请日：1996-12-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  GILLIAM, Gary, R. ,  DUESMAN, Kevin, G. ,  NEVILL, Leland, R.

IPC: G06F11/20

CPC classification number: G11C29/80 ,  G11C29/808

Abstract: A memory device module in a package having externally accessible contacts includes multiple integrated memory circuits accessible to external circuitry exclusively through the contacts. An accessing circuit for each memory circuit accesses memory cells in the memory circuit for communication with the external circuitry. Each accessing circuit can be enabled to access redundant memory cells instead of inoperative memory cells by an enabling signal. An enabling circuit for each accessing circuit can output the enabling signal in response to receiving a unique set of input signals from external circuitry. Each unique set is selected with fuses in each enabling circuit, and includes row and column address strobe signals and a data signal. Upon receiving its unique set, one of the enabling circuits advantageously enables its associated accessing circuit to access redundant memory cells without the accessing circuits of the other memory circuits also being so enabled.

Abstract translation: 具有外部可访问触点的封装中的存储器件模块包括仅通过触点对外部电路可访问的多个集成存储器电路。 每个存储器电路的访问电路访问存储器电路中的存储器单元以与外部电路通信。 可以通过使能信号使每个访问电路能够访问冗余存储器单元而不是不工作的存储器单元。 每个访问电路的使能电路可以响应于从外部电路接收到一组唯一的输入信号而输出使能信号。 每个独特的集合在每个使能电路中选择熔丝，并包括行和列地址选通信号和数据信号。 在接收到其唯一的集合之后，启用电路之一有利地使其相关联的访问电路访问冗余存储器单元，而其他存储器电路的访问电路也被启用。

公开(公告)号：WO1997023907A1

公开(公告)日：1997-07-03

申请号：PCT/US1996020300

申请日：1996-12-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  PRALL, Kirk ,  STONE, Tod ,  ZAGAR, Paul, S.

IPC: H01L23/525

CPC classification number: G11C29/785 ,  G11C29/80 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A configuration for a laser fuse bank is disclosed wherein the available space is more efficiently used. Fuses (101, 102, 103) of graduated width and variable configuration are placed so as to minimize the average distance between fuses and maximize fuse density. Alternatively, a common source is added to a standard laser fuse structure such that it intersects the fuses and the number of available fuses is doubled.

Abstract translation: 公开了一种用于激光熔丝排的配置，其中可用空间被更有效地使用。 放置具有分级宽度和可变结构的熔丝（101,102,103），以使熔丝之间的平均距离最小化并使熔丝密度最大化。 或者，将公共源添加到标准激光熔丝结构中，使得其与保险丝相交，并且可用熔丝的数量加倍。