公开(公告)号：US11899948B2

公开(公告)日：2024-02-13

申请号：US17984118

申请日：2022-11-09

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  James P. Crowley ,  Jiangang Wu ,  Peng Xu

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.

公开(公告)号：US11868202B2

公开(公告)日：2024-01-09

申请号：US17946328

申请日：2022-09-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qisong Lin ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Shao Chun Shi

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/073 ,  G06F11/0751

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write a plurality of flag bits within a group of memory cells programmed by the multi-pass programming command. The system also includes a processing device, operatively coupled to the memory component. The processing device is to detect an error in attempting to read a top page of the group of memory cells, determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error due to the top page of the group of memory cells being incompletely programmed.

公开(公告)号：US11841794B2

公开(公告)日：2023-12-12

申请号：US17536928

申请日：2021-11-29

Applicant: Micron Technology, Inc.

Inventor： Karl D. Schuh ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Kishore K. Muchherla

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/0882 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/064 ,  G06F3/0614 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0882 ,  G06F2212/7201

Abstract: A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.

公开(公告)号：US11693774B2

公开(公告)日：2023-07-04

申请号：US17412225

申请日：2021-08-25

Applicant: Micron Technology, inc.

Inventor： Jiangang Wu ,  Jing Sang Liu ,  Jung Sheng Hoei ,  Kishore Kumar Muchherla ,  Mark Ish ,  Myoung Jun Go ,  Nolan Tran ,  Qisong Lin

IPC: G06F12/00 ,  G06F12/0806

CPC classification number: G06F12/0806 ,  G06F2212/1024 ,  G06F2212/603

Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.

公开(公告)号：US20230071878A1

公开(公告)日：2023-03-09

申请号：US17984118

申请日：2022-11-09

Applicant: Micron Technology, Inc.

Inventor： Yun Li ,  James P. Crowley ,  Jiangang Wu ,  Peng Xu

IPC: G06F3/06

Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.

公开(公告)号：US20230065231A1

公开(公告)日：2023-03-02

申请号：US17412225

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Jing Sang Liu ,  Jung Sheng Hoei ,  Kishore Kumar Muchherla ,  Mark Ish ,  Myoung Jun Go ,  Nolan Tran ,  Qisong Lin

IPC: G06F12/0806

Abstract: A method is described, which includes receiving, by a memory subsystem, a memory command targeted at a memory array; determining, by the memory subsystem, if the memory command is a high priority memory command; and determining if the memory subsystem is processing any non-high priority memory commands. The memory subsystem enables a read page cache mode for processing the memory command in response to determining that (1) the memory command is a high priority memory command and (2) the memory subsystem is not processing any non-high priority memory commands Thereafter, the memory subsystem processes the memory command using the read page cache mode.

公开(公告)号：US11500564B2

公开(公告)日：2022-11-15

申请号：US17153233

申请日：2021-01-20

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Peter Feeley ,  Karl D. Schuh

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04

Abstract: A block family associated with a memory device is initialized. An initial value of a power cycle count associated with the memory device is stored. Responsive to programming a block residing in the memory device, the block is associated with the block family. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, the block family is closed. Responsive to determining that a time period that has elapsed since initializing the block family exceeds a threshold period, the block family is closed.

公开(公告)号：US11450391B2

公开(公告)日：2022-09-20

申请号：US16948359

申请日：2020-09-15

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Jiangang Wu ,  Devin M. Batutis ,  Xiangang Luo

IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G11C16/04

Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

公开(公告)号：US20220283952A1

公开(公告)日：2022-09-08

申请号：US17824676

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Abdelhakim Alhussien ,  Jiangang Wu ,  Karl D. Schuh ,  Qisong Lin ,  Jung Sheng Hoei

IPC: G06F12/0882 ,  G06F12/02 ,  G11C11/408 ,  G06F9/30 ,  G06F9/4401

Abstract: A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

公开(公告)号：US11437111B2

公开(公告)日：2022-09-06

申请号：US17122758

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, Jr. ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Kishore K. Muchherla ,  Gil Golov ,  Todd A. Marquart ,  Jiangang Wu ,  Niccolo' Righetti ,  Ashutosh Malshe

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/26

Abstract: Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.