公开(公告)号：DE69100003D1

公开(公告)日：1992-10-15

申请号：DE69100003

申请日：1991-01-07

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： SOURGEN LAURENT

IPC: G01R31/317 ,  G06F12/14 ,  G07F7/10 ,  G11C29/24 ,  G11C29/52

Abstract: The invention relates to integrated circuits, and more particularly those which use electronic latches in order to modify the configuration of the circuit, for example to restrain access by the user to certain functions or certain data of the circuits. … According to the invention, a first electronic latch (CL1, CL'1, X1) is provided which is able to be locked or unlocked during a phase of testing the integrated circuit and to be irreversibly locked after the end of the test phase, and a second electronic latch (CL2, CL'2, X2) able to be unlocked only when the first latch is unlocked. In this way, the whole of the integrated circuit can be tested as it is presented for the user, the locking of the latches being in some way simulated during testing.

公开(公告)号：DE3867810D1

公开(公告)日：1992-02-27

申请号：DE3867810

申请日：1988-11-18

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： SOURGEN LAURENT ,  LISIMAQUE GILLES ,  DEVIN JEAN

IPC: G11C14/00 ,  G11C11/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

Abstract: In order to avoid technological differentiation between random- access memory cells and read-only memory cells of a single memory plane, all the memory cells are produced with a single technology. These memory cells are then essentially composed of floating-gate transistors. Programming of the random-access memory cells is done, conventionally, by injecting, or not, electronic charges into the floating gates of the transistors. The programming (IM, Im), or not, of the read-only memory cells is done by implanting impurities (^I) into the conduction channels of the floating-gate transistors of these memory cells. It is shown that concealment is improved of the contents of the read-only memory cells which contents are intended to remain hidden, whilst improving the conditions for producing prototypes on request. … …

公开(公告)号：DE68900160D1

公开(公告)日：1991-08-29

申请号：DE68900160

申请日：1989-11-02

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FRUHAUF SERGE ,  SOURGEN LAURENT

IPC: G06F12/14 ,  G06F21/06 ,  G06K19/073 ,  G07F7/10 ,  G11C7/24 ,  G11C16/22 ,  G11C16/06 ,  G11C7/00

Abstract: The disclosure concerns the safety of the confidential information contained in integrated circuits. In a certain number of integrated circuit applications and, more particularly, in the circuits contained in cards known as "chip cards", it is necessary to prohibit access by unauthorized persons to confidential information stored in a memory of the circuit. To prevent the fraudulent practice of examining the current consumption at the terminals of the integrated circuit during an operation of reading or writing in the memory, a protection circuit is used. This protection circuit actuates the simulation, according to a pseudo-random sequence generated by a generator, of current consumption values identical to those of real memory cells.

公开(公告)号：FR2748616B1

公开(公告)日：1998-06-12

申请号：FR9605719

申请日：1996-05-07

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： LISART MATHIEU ,  SOURGEN LAURENT

IPC: G11C16/12 ,  H03K4/00 ,  G11C7/06

Abstract: The circuit comprises a voltage booster which produces a high DC output. A control circuit uses this to generate a ramped programming voltage. The source of a first P-type load transistor is connected to the output of the voltage booster. Its drain is coupled to a capacitor and by its gate to the control circuit. The high voltage programming output is produced at the transistor drain. The control circuit includes a pulse generator which applies a stepped voltage to the load transistor gate. The capacitor is formed by line of bits in a memory map. The control circuit also comprises a P-type transistor which is mounted in diode configuration and is used to charge the capacitor with a constant current.

公开(公告)号：DE69600148D1

公开(公告)日：1998-02-26

申请号：DE69600148

申请日：1996-03-19

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： SOURGEN LAURENT ,  WUIDART SYLVIE

IPC: G11C17/00 ,  G11C7/00 ,  G11C16/02 ,  G11C16/22 ,  G11C16/06

Abstract: The method involves using a high-voltage generator (1) and regulator (2) delivering the write pulse (Ve) to the memory address decoder (5) in response to a command (3) from a counter (9) initialised by a pseudo-random number generator (8). A microprocessor ( mu p) decodes a write instruction received via input/output signals (IO1,IO2) and reads the random number which is decremented to 1 at the rate of the clock (Clk). A constant delay between the external write command and the end-of-write signal is held in a memory (10) which activates another counter (11) and is programmed for each circuit.

公开(公告)号：FR2740553B1

公开(公告)日：1997-12-05

申请号：FR9512659

申请日：1995-10-26

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE ,  SOURGEN LAURENT

IPC: H01L21/66 ,  H01L21/82 ,  H01L23/58 ,  G01R31/28 ,  G01R27/28

Abstract: The detection circuit has a pulse generator, which has a counter incrementing the pulse length of each pulse sent out. The pulse (Se) is applied to the integrated circuit via a snake shaped metallising line (2). The line forms a pass band filter with the passivation layer, and thus the short pulses are not received at the receiver (Sd) whilst longer pulses are. A correctly passivated integrated circuit can thus be determined from a tolerance threshold around the critical cut off pulse lengths.

公开(公告)号：FR2740553A1

公开(公告)日：1997-04-30

申请号：FR9512659

申请日：1995-10-26

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE ,  SOURGEN LAURENT

IPC: H01L21/66 ,  H01L21/82 ,  H01L23/58 ,  G01R31/28 ,  G01R27/28

Abstract: The detection circuit has a pulse generator, which has a counter incrementing the pulse length of each pulse sent out. The pulse (Se) is applied to the integrated circuit via a snake shaped metallising line (2). The line forms a pass band filter with the passivation layer, and thus the short pulses are not received at the receiver (Sd) whilst longer pulses are. A correctly passivated integrated circuit can thus be determined from a tolerance threshold around the critical cut off pulse lengths.

公开(公告)号：FR2723223B1

公开(公告)日：1996-08-30

申请号：FR9409485

申请日：1994-07-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： WUIDART SYLVIE ,  SOURGEN LAURENT

IPC: G06F1/00 ,  G06F7/76 ,  G06F21/22 ,  G06F21/00 ,  G09C1/00 ,  H01L27/10 ,  G06F12/14 ,  H03M7/00

Abstract: The method involves using an executable code generator for discriminating between program instructions and program data, and for bit-scrambling the instructions. The resulting code is loaded into a programmable memory connected by the data bus to a controller. Program code is sent in scrambled form over the data bus, and is de-scrambled by a controller (DBR1,RI) for delivery to a processor (UP). A re-writable memory clears data, which is carried on the data bus and scrambles (DBR2,DBR3) data for storage. The data is unscrambled when read from storage. The scrambling algorithms for program code and for data are different.

公开(公告)号：FR2728363A1

公开(公告)日：1996-06-21

申请号：FR9415347

申请日：1994-12-20

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： LISART MATHIEU ,  SOURGEN LAURENT

IPC: G06F12/14 ,  G06F21/02 ,  G06K17/00 ,  G06K19/073

Abstract: The system includes a microprocessor(1), a memory bank(2- 9) containing words(17), a transmission bus(15) for sending data, address and control information between the microprocessor and the memory bank, and an access protection circuit(18). The access protection circuit contains a decision table(18), circuits(19) for addressing the table(18), with the addresses of the memory words. A protection circuit(31-33) which produces a protection signal as a function of a read of the decision table. It allots(14) to certain words to be protected(17) an arrangement of control bits(21) , a circuit(22) to read these control bits at the time (LEC) of reading these words, and a circuit(23-25) to address the decision table as a function of the value of the bits read.

公开(公告)号：DE69300009T2

公开(公告)日：1995-05-11

申请号：DE69300009

申请日：1993-04-22

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： FOURNEL RICHARD PIERRE ,  SOURGEN LAURENT

IPC: G01R19/165 ,  G06F1/28 ,  H03K17/22

Abstract: The invention relates to a circuit for detecting voltage threshold crossing, principally making it possible to detect a threshold of a voltage of an integrated circuit. A circuit is proposed which includes two capacitors (C1, C2), and a set of switches (K1, K2, K3) actuated periodically and configured so as: - in a first phase (H) to apply the input voltage to the terminals of the first capacitor (C1) and to apply the voltage of the second capacitor (C2) to the gate of a detection transistor (T1), the two capacitors being insulated from one another, - in a second phase to connect the two capacitors so as to charge the second by the first, the capacitors being insulated from the input (E) and from the gate of the detection transistor, the circuit furthermore including a means (T2) for precharging the drain of the detection transistor (T1) during the first phase, a means (R) for discharging the second capacitor during the first phase (H), and a circuit (I, T3) for latching the logic level of the drain of the detection transistor.