公开(公告)号：DE69935066D1

公开(公告)日：2007-03-22

申请号：DE69935066

申请日：1999-05-03

Applicant: ST MICROELECTRONICS SA

Inventor： WOJCIESZAK LAURENT ,  COFLER ANDREW

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/318

Abstract: A prefetch buffer is described which supports a computer system having a plurality of different instruction modes. The number of storage locations which are read out of the prefetch buffer during each machine cycle is controlled in dependence on the instruction mode. Thus the prefetch buffer allows a number of different instruction modes to be supported and hides memory access latency.

公开(公告)号：FR2881869A1

公开(公告)日：2006-08-11

申请号：FR0550338

申请日：2005-02-04

Applicant: ST MICROELECTRONICS SA

Inventor： DRUILHE FRANCOIS ,  COFLER ANDREW ,  DUTOIT DENIS ,  HARRAND MICHEL ,  EYZAT GILLES ,  FREUND CHRISTIAN

IPC: G11C11/406 ,  H04M19/08 ,  H04Q7/32

Abstract: L'invention concerne une mémoire dynamique (50) et son application à un circuit de téléphonie mobile avec un circuit de commande comportant un premier contrôleur de rafraîchissement (48) commandé par un premier signal d'horloge (CKIN) et un deuxième contrôleur de rafraîchissement (58) commandé par un deuxième signal d'horloge (LCK) de fréquence inférieure au premier et utilisé pour synchroniser des événements du réseau GSM.

公开(公告)号：FR2856814A1

公开(公告)日：2004-12-31

申请号：FR0307689

申请日：2003-06-25

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW

IPC: G06F12/08 ,  G06F12/0864 ,  G06F12/12 ,  G06F12/126

公开(公告)号：GB2365546B

公开(公告)日：2004-02-18

申请号：GB9930586

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  WOJCIESZAK LAURENT ,  SENAME ISABELLE

IPC: G06F11/36

Abstract: A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be "killed" later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.

公开(公告)号：FR2821449B1

公开(公告)日：2003-07-04

申请号：FR0102647

申请日：2001-02-27

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is stored in the first FIFO-type memory, and other operative instructions are stored in the second FIFO-type memory. An operative instruction involving the register is removed from the second FIFO-type memory if no loading instruction which is earlier in time, and intended to modify a value of the register associated with this operative instruction is present in the first FIFO-type memory. In the presence of such an earlier loading instruction, the operative instruction is removed from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.

公开(公告)号：FR2821449A1

公开(公告)日：2002-08-30

申请号：FR0102647

申请日：2001-02-27

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is stored in the first FIFO-type memory, and other operative instructions are stored in the second FIFO-type memory. An operative instruction involving the register is removed from the second FIFO-type memory if no loading instruction which is earlier in time, and intended to modify a value of the register associated with this operative instruction is present in the first FIFO-type memory. In the presence of such an earlier loading instruction, the operative instruction is removed from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.

公开(公告)号：GB2366006A

公开(公告)日：2002-02-27

申请号：GB9930587

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  WOJCIESZAK LAURENT ,  SENAME ISABELLE

IPC: G06F9/38 ,  G06F11/36

Abstract: A computer system where step-by-step execution of an instruction sequence is implemented, each instruction including a guard value. The guard value determines whether the instruction is executed. If after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is non-committed the next instruction in the sequence is executed. The system includes a pipelined execution unit and an emulation unit. The application discloses both a system and a method of execution. Also disclosed is a computer system where a decode unit is set in a stall state, either by reading stall attributes associated with debug instructions or in response to a stall command from an on-chip emulation unit. A method is also described.

公开(公告)号：GB2365546A

公开(公告)日：2002-02-20

申请号：GB9930586

申请日：1999-12-23

Applicant: ST MICROELECTRONICS SA

Inventor： COFLER ANDREW ,  WOJCIESZAK LAURENT ,  SENAME ISABELLE

IPC: G06F11/36

Abstract: A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be "killed" later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.