公开(公告)号：DE60109958D1

公开(公告)日：2005-05-12

申请号：DE60109958

申请日：2001-11-14

Applicant: ST MICROELECTRONICS SA

Inventor： CAVALERI PAOLA ,  LECONTE BRUNO ,  ZINK SEBASTIEN ,  DEVIN JEAN

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/16 ,  G11C16/34

Abstract: The present invention relates to a page-erasable FLASH memory including a memory array having a plurality of pages each with floating-gate transistors connected by their gates to word lines, a word line decoder connected to the word lines of the memory, and the application of a positive erase voltage to the source or drain electrodes of all the floating-gate transistors of a sector forming a page to be erased. According to the present invention, the word line decoder includes a unit for applying, when a page is being erased, a negative erase voltage to the gates of the transistors of the page to be erased, while applying a positive inhibit voltage to the gates of the transistors of at least one page that is not to be erased.

公开(公告)号：FR2856186A1

公开(公告)日：2004-12-17

申请号：FR0307052

申请日：2003-06-12

Applicant: ST MICROELECTRONICS SA

Inventor： LECONTE BRUNO ,  CAVALERI PAOLA ,  ZINK SEBASTIEN

IPC: G11C16/34

公开(公告)号：FR2856185A1

公开(公告)日：2004-12-17

申请号：FR0307050

申请日：2003-06-12

Applicant: ST MICROELECTRONICS SA

Inventor： LECONTE BRUNO ,  CAVALERI PAOLA ,  ZINK SEBASTIEN

IPC: G11C16/10

Abstract: The memory has a sequencer (SEQ2) to store sequence of external words in a buffer memory (BMEM2). The sequencer stores internal words present in the page in the buffer memory, erases the page and stores words present in the buffer memory in the erased page. The page is formed by memory cell in a main memory (FMEM2). The buffer memory has the external words and the internal words. An independent claim is also included for a method for storing sequence of external words in a target page of a main memory.

公开(公告)号：FR2851074A1

公开(公告)日：2004-08-13

申请号：FR0301558

申请日：2003-02-10

Applicant: ST MICROELECTRONICS SA

Inventor： CAVALERI PAOLA ,  ZINK SEBASTIEN ,  LECONTE BRUNO

IPC: G11C11/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/14 ,  G11C16/16 ,  G11C16/34

Abstract: Memory (MEM1) has memory plan organized into sectors (ST1-ST8), each with counter (CMPT1-CMPT8) of control and refreshment which is integrated in sector. Sector has memory cells linked to lines of bit of sector. Control and refreshment units are arranged to erase counter after reaching maximum count value chosen so that when maximal count value is reached, memory cells have undergone number of electric stress cycles equal to determined value. An independent claim is also included for a method for controlling and refreshing the memory cells in a electrically erasable and programmable memory.

公开(公告)号：FR2805653A1

公开(公告)日：2001-08-31

申请号：FR0002449

申请日：2000-02-28

Applicant: ST MICROELECTRONICS SA

Inventor： CAVALERI PAOLA ,  LECONTE BRUNO ,  ZINK SEBASTIEN

IPC: G11C7/10 ,  G11C8/00 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C7/00 ,  G11C16/02

Abstract: The memory in the form of an integrated circuit (MEM1) has an input (DIN) and an output (DOUT) in series and comprises means including a multiplexer (MEX1) for data reading on the reception of a partial address (ADR1) wherein N low-value bits are missing with respect to a complete address. The advanced reading operation comprises the following steps: the simultaneous reading of P first bits, that is P1(W0), P1(W1), ..., P1(WM), of M binary words (W0,W1,...WM) of the memory with the same partial address, when the received address is complete, that is comprising (ADR1,ADR2), the selection of P first bits of word indicated by the complete address and the delivery of these bits to the output, and the reading of subsequent P bits of word indicated by the complete address during the delivery of P preceding bits, and the delivery of the subsequent bits to the output when the preceding bits are delivered. The reading of P subsequent bits is effected like the reading of first P bits, that is by simultaneous reading of subsequent bits of words having the same partial address, and the selection of subsequent bits of word indicated by the complete address. The reading operation is effected by applying the partial address to a decoder and by scanning the low-value address inputs allowing for 2N possible combinations of N low-value bits (A0,A1,...AN-1). A memory unit comprising cells laid out according to word lines and bit lines, where the bit lines are laid out in columns, also comprises an address decoder for the simultaneous selection of P bit lines of M columns, and an interconnection bus for connecting the selected bit lines to the reading circuits, that is sense amplifiers. A memory unit comprises cells laid out according to word lines and bit lines, where a word line forms a page memory, and the reading operation comprises a preliminary step which includes the registering of M words of the same partial address in M adjacent sub-pages, of each word in P adjacent sets of cells, each comprising K/P adjacent subsets of cells, where K is the number of bits of each word, and of bits of rank j and j+1 of word in sets of adjacent cells, and of rank j and j+P of word in subsets of adjacent cells, so that the words are folded in the sub-pages. The number P is equal to K/M where M is equal to 2N; in particular, N = 1, and M = 2. The P first bits of each word are high-value bits. The address decoder comprises transistors for the selection of bit lines, a programming circuit comprising M times K latches connected to the input of data bus having K leads, and also the means for the inhibition of N low-value address inputs in reading mode. A multiplexer in memory unit with subsets of cells is controlled by a scanning circuit. A memory unit comprising a block memory and peripheral elements, also comprises the means for interlacing bits in the form of random-access memory positioned between the data input and the block input, to form composite words comprising M sets of P bits of M different binary words. The memory also comprises means for registering composite words in a buffer memory.

公开(公告)号：DE69900032T2

公开(公告)日：2001-03-22

申请号：DE69900032

申请日：1999-05-26

Applicant: ST MICROELECTRONICS SA

Inventor： MOREAUX CHRISTOPHE ,  LECONTE BRUNO

IPC: G11C7/10 ,  G11C7/00

Abstract: The integrated circuit (1) comprises two memory units (MEM1,MEM2) connected to an input/output (E/S) bus (2), external and internal address buses (3,4). A redirection circuit and the first memory unit are configurable according to two formats with inputs of a selection signal (Sel). The first memory unit, which is configurable according to two different formats, is of much higher capacity than the second memory unit of a fixed format, e.g. 16 bits and 8 bits formats. A variant of the device comprises inputs of two selection signals to the memory units and to the redirection circuit, or two redirection circuits with separate inputs of the selection signals. The redirection circuit contains one or two multiplexers controlled by the selection signal, or four multiplexers and two ports for the input of two selection signals.