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    INPUT CIRCUIT FOR MEMORY SMART CARD
    1.
    发明专利
    INPUT CIRCUIT FOR MEMORY SMART CARD 失效

    公开(公告)号：JP2001229664A

    公开(公告)日：2001-08-24

    申请号：JP2000296390

    申请日：2000-09-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： MOREAUX CHRISTOPHE

    IPC: G06K19/07 ,  G11C7/00

    Abstract: PROBLEM TO BE SOLVED: To eliminate the danger that a card fails because of a contact defect between the card and the brush of a card reader. SOLUTION: This input circuit 200 for a memory integrated circuit receives a first binary signal SA transmitted by the direct contact of the card and the reader 150, performs change by first binary data A and outputs a write control signal WR for controlling a memory 140. The input circuit is provided with a control circuit 220 for inspecting the voltage level of the first binary signal SA and outputting a confirmation signal VAL and an inhibition circuit 240 for inhibiting a write command WR when the confirmation signal VAL is inactive.

    METHOD OF CONFIGURING A MEMORY SPACE THAT IS DIVIDED INTO MEMORY AREAS
    2.
    发明申请
    METHOD OF CONFIGURING A MEMORY SPACE THAT IS DIVIDED INTO MEMORY AREAS 审中-公开
    配置一个划分为记忆区域的存储空间的方法

    公开(公告)号：WO2007023213A3

    公开(公告)日：2007-04-12

    申请号：PCT/FR2006001768

    申请日：2006-07-19

    Applicant: ST MICROELECTRONICS SA ,  MOREAUX CHRISTOPHE ,  KARI AHMED ,  NAURA DAVID ,  RIZZO PIERRE

    Inventor： MOREAUX CHRISTOPHE ,  KARI AHMED ,  NAURA DAVID ,  RIZZO PIERRE

    IPC: G06F12/02

    CPC classification number: G06F12/0292

    Abstract: The invention relates to a method of configuring a memory space (MEM), comprising the following steps consisting in: reading a configuration datum (SZ3) in the memory space (MEM) and dividing at least part of the memory space into memory areas (Z1-Z4) as a function of the configuration datum read; and assigning each memory area with an access number (NBK) that is used to access a datum location in the memory area, together with a logical address of the location in the memory area. The invention is suitable for RFID chips.

    Abstract translation: 本发明涉及一种配置存储空间（MEM）的方法，包括以下步骤：读取存储空间（MEM）中的配置数据（SZ3），并将至少部分存储空间划分为存储区域（Z1 -Z4）作为配置数据读取的函数; 以及为每个存储区域分配用于访问存储区域中的数据位置的访问号码（NBK）以及存储区域中的位置的逻辑地址。 本发明适用于RFID芯片。

    3.
    发明专利
    未知

    公开(公告)号：DE602005010935D1

    公开(公告)日：2008-12-24

    申请号：DE602005010935

    申请日：2005-05-17

    Applicant: ST MICROELECTRONICS SA

    Inventor： MOREAUX CHRISTOPHE ,  RIZZO PIERRE

    IPC: G06K7/00

    Abstract: The method involves transmitting only once, a word group reading order from a start address to a tag. An address register of the tag is initialized to a value of the address to which the word is then transmitted. An incrementation HTML tag is transmitted to the tag, and the register is then incremented. A data frame with a word stored at address indicated by register`s current value is transmitted towards a remote interrogation unit. An independent claim is also included for a contactless tag.

    PROCEDE D'ECRITURE PAR BLOC DANS UNE MEMOIRE
    5.
    发明专利
    PROCEDE D'ECRITURE PAR BLOC DANS UNE MEMOIRE 未知

    公开(公告)号：FR2891653A1

    公开(公告)日：2007-04-06

    申请号：FR0510158

    申请日：2005-10-05

    Applicant: ST MICROELECTRONICS SA

    Inventor： KARI AHMED ,  MOREAUX CHRISTOPHE ,  NAURA DAVID ,  RIZZO PIERRE

    IPC: G11C16/10 ,  G06K7/08 ,  G06K19/073

    Abstract: L'invention concerne un procédé d'écriture par bloc dans une mémoire non volatile programmable électriquement, un bloc à écrire dans la mémoire comprenant au moins un mot. Selon l'invention, le procédé comprend des étapes de détermination d'une durée d'écriture d'un mot en divisant une durée fixée d'écriture d'un bloc par le nombre de mots du bloc à écrire, et de commande de la mémoire pour écrire successivement chaque mot (D) dans la mémoire pendant la durée d'écriture.

    Configurable electronic circuit, has non-modifiable circuit for selective application of supply potential, and modifiable circuit comprising fusible, for each node
    7.
    发明专利
    Configurable electronic circuit, has non-modifiable circuit for selective application of supply potential, and modifiable circuit comprising fusible, for each node 未知

    公开(公告)号：FR2787912A1

    公开(公告)日：2000-06-30

    申请号：FR9816367

    申请日：1998-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： MOREAUX CHRISTOPHE

    IPC: H01L27/118 ,  H03K19/173 ,  G11C17/14 ,  H03H3/00 ,  H03H11/00

    Abstract: The circuit comprises a set of nodes or terminals (N1-Nn). For each node there is a corresponding set of non-modifiable circuits (MF1-MFn) for selectively applying one of two supply potentials (Vdd,Gnd), to the configuration nodes. There is also a set of modifiable circuits (MM1-MMn) for modifying the potential applied to the configuration nodes by non-modifiable circuits. The modifiable circuit (MMi) comprises a fusible (Fi), which is in an intact state before configuring, and in a breakdown state after configuring. This is connected so that Gnd potential is applied to the node in the intact state, and Vdd potential is applied to the node in the breakdown state. The two potentials are the ground or earth potential (Gnd), and the positive supply potential (Vdd). The modifiable circuit (MFi) contains several p inverters connected in series, where p is an even number, e.g. p = 2, and a junction (JCi) connecting the node to the output of the pth inverter, or to the output of the qth inverter, where q is an odd number, e.g. q = 1, which is less than p. The fusible (Fi) is connected in series with an interrupter component between terminals receiving the first potential (Gnd) and the second potential (Vdd). The common node is connected to the input of the first inverter (I1i) of the modifiable circuit (MFi). The interrupter component is a MOS transistor (MP1i), with its drain connected to the gate via an inverter (FBi). The MOS transistor (MP1i) forming an interrupter is of p-type, and its source is connected to the supply terminal. Its drain is joined to ground potential (Gnd) via the fusible (Fi). A second MOS transistor of p-type (MP2i) is connected in parallel with the MOS transistor forming an interrupter (MP1i), and receives transitionally a voltage delivered by a Power On Reset (POR) block.

    8.
    发明专利
    未知

    公开(公告)号：DE602006000534T2

    公开(公告)日：2009-02-19

    申请号：DE602006000534

    申请日：2006-08-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： NAURA DAVID ,  KARI AHMED ,  MOREAUX CHRISTOPHE ,  RIZZO PIERRE

    IPC: G11C16/22

    Abstract: The circuit has a memory (MEM1) containing transaction data, with electrically erasable and programmable memory cells (C i, j) arranged in horizontal and vertical lines, and linked to word lines (WL i) and bit lines (BL j). A control unit (CTU) executes commands for reading or writing in the memory. The CTU is blocked when reference memory cells of one of the groups contain bits of equal value and if the value is different from a value expected for the one of the groups. The CTU controls a voltage generator (VGEN) which supplies a read voltage (Vread) and an erase-programming voltage (Vpp). An independent claim is also included for a method for protecting an integrated circuit against a global data erasure.

    9.
    发明专利
    未知

    公开(公告)号：DE602006000534D1

    公开(公告)日：2008-03-27

    申请号：DE602006000534

    申请日：2006-08-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： NAURA DAVID ,  KARI AHMED ,  MOREAUX CHRISTOPHE ,  RIZZO PIERRE

    IPC: G11C16/22

    Abstract: The circuit has a memory (MEM1) containing transaction data, with electrically erasable and programmable memory cells (C i, j) arranged in horizontal and vertical lines, and linked to word lines (WL i) and bit lines (BL j). A control unit (CTU) executes commands for reading or writing in the memory. The CTU is blocked when reference memory cells of one of the groups contain bits of equal value and if the value is different from a value expected for the one of the groups. The CTU controls a voltage generator (VGEN) which supplies a read voltage (Vread) and an erase-programming voltage (Vpp). An independent claim is also included for a method for protecting an integrated circuit against a global data erasure.

    PROCEDE ET DISPOSITIF DE VERIFICATION DE L'EXECUTION D'UNE COMMANDE D'ECRITURE DANS UNE MEMOIRE
    10.
    发明专利
    PROCEDE ET DISPOSITIF DE VERIFICATION DE L'EXECUTION D'UNE COMMANDE D'ECRITURE DANS UNE MEMOIRE 未知

    公开(公告)号：FR2894710A1

    公开(公告)日：2007-06-15

    申请号：FR0512631

    申请日：2005-12-14

    Applicant: ST MICROELECTRONICS SA

    Inventor： KARI AHMED ,  MOREAUX CHRISTOPHE ,  NAURA DAVID ,  RIZZO PIERRE

    IPC: G11C29/52 ,  G11C7/24

    Abstract: L'invention concerne un procédé d'exécution d'une commande d'écriture d'un mot binaire dans une mémoire programmable, comprenant des étapes d'écriture de chacun des bits (RB) dans un état programmé d'un mot binaire à écrire (D) dans une cellule mémoire correspondante de la mémoire, de lecture de chaque bit (MB) du mot écrit dans la mémoire (MEM) correspondant à un bit (RB) à l'état programmé du mot à écrire, de comparaison de chaque bit (RB) à l'état programmé du mot à écrire à un bit correspondant (MB) lu dans la mémoire, et de génération d'un signal d'erreur (ER) si au moins un bit du mot à écrire à l'état programmé est différent du bit correspondant lu. Application de l'invention notamment aux circuits intégrés pour carte à puce.

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