23.
    发明专利
    未知

    公开(公告)号:AT387771T

    公开(公告)日:2008-03-15

    申请号:AT05290013

    申请日:2005-01-05

    Abstract: A data communication device comprises an input circuit (DRTC) that converts external data (XDT) into internal data (IDT) on the basis of a sampling signal (SP). A synchronization circuit (SYNC) provides the sampling signal (SP) on the basis of an oscillator signal (OS) and a synchronization value (SV). The synchronization value (SV) is representative of a number of cycles of the oscillator signal (OS) contained within a time interval for a unit of external data. The synchronization value (SV) is an initial value (IV) during an initial synchronization phase and a measured value (MV) during a measurement-based synchronization phase. A control circuit (IFC) carries out a calibration step in which the initial value (IV) is a preprogrammed reset value (RV) and in which the measured value (MV) is stored as a calibration value (CV). The control circuit (IFC) applies the calibration value (CV) as the initial value (IV) in subsequent initial synchronization phases.

    24.
    发明专利
    未知

    公开(公告)号:DE60128608T2

    公开(公告)日:2008-01-31

    申请号:DE60128608

    申请日:2001-01-24

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    PROTECTION DE L'EXECUTION D'UN PROGRAMME

    公开(公告)号:FR2888370A1

    公开(公告)日:2007-01-12

    申请号:FR0552047

    申请日:2005-07-05

    Abstract: L'invention concerne un procédé de protection de l'exécution d'un programme principal (Pg) contre d'éventuels déroutements, comporte les étapes de, lors d'une instruction du programme principal, déclencher un compteur temporel (TIMER) d'un compte donné en fonction d'instructions qui suivent du programme principal, et exécuter une fois que le compteur a atteint son compte au moins une instruction d'un programme secondaire dont dépend le résultat du programme principal.

    26.
    发明专利
    未知

    公开(公告)号:DE60118815T2

    公开(公告)日:2006-11-30

    申请号:DE60118815

    申请日:2001-01-17

    Inventor: POMET ALAIN

    Abstract: The delay ( delta 1, delta 2) between two sync pulses, calculated with respect to internal time unit (ut), is measured with respect to preceding pulse of clock signal (CK100). The two delays, a measure of the number of reference clock periods and of the number of clock pulses (N), are applied to start a computer (10) which calculates a corresponding period (T6) and to initialize stop counting (C2) activated at each regen. cycle so as to output a regenerated clock pulse (CKGEN). Clock signal regeneration from at least two synchronizing pulses (IS1,IS2) transmitted on an external USB bus, in an integrated circuit (C1) having an internal oscillator (2) designed to provide a reference clock signal (CK100). A unit (130) defines a unit of time (ut) and an associated measuring unit (131) provides a precise measure in the time unit of the delay between two synchronizing pulses each with respect to a preceding reference clock signal (CK100). The definition unit (130) includes a train of delay circuits (P0,P1,....) at the input of which is applied the reference clock signal (CK100). The delay applied by each circuit being equal to the time unit (ut). The measuring unit (131) includes a flip flop (B0) by the delay circuit (P0) and a read register (RL). The input of delay circuit being applied as input (D) of the associated flip flop, whose output )Q) is applied on a corresponding input of the read register.

    27.
    发明专利
    未知

    公开(公告)号:DE69817928D1

    公开(公告)日:2003-10-16

    申请号:DE69817928

    申请日:1998-07-03

    Abstract: A sequential access memory consists of a number (N) of recording elements, each memorising one bit of information and distributed into P groups, each of L elements. In an initial operating phase, with a duration corresponding to P-1 consecutive clock signal periods, only the last element in each group, connected in series, is activated. During a second operating phase, with a duration corresponding to a single clock signal period, all the elements are activated.

    28.
    发明专利
    未知

    公开(公告)号:FR2803925B1

    公开(公告)日:2002-03-15

    申请号:FR0000605

    申请日:2000-01-18

    Inventor: POMET ALAIN

    Abstract: The delay ( delta 1, delta 2) between two sync pulses, calculated with respect to internal time unit (ut), is measured with respect to preceding pulse of clock signal (CK100). The two delays, a measure of the number of reference clock periods and of the number of clock pulses (N), are applied to start a computer (10) which calculates a corresponding period (T6) and to initialize stop counting (C2) activated at each regen. cycle so as to output a regenerated clock pulse (CKGEN). Clock signal regeneration from at least two synchronizing pulses (IS1,IS2) transmitted on an external USB bus, in an integrated circuit (C1) having an internal oscillator (2) designed to provide a reference clock signal (CK100). A unit (130) defines a unit of time (ut) and an associated measuring unit (131) provides a precise measure in the time unit of the delay between two synchronizing pulses each with respect to a preceding reference clock signal (CK100). The definition unit (130) includes a train of delay circuits (P0,P1,....) at the input of which is applied the reference clock signal (CK100). The delay applied by each circuit being equal to the time unit (ut). The measuring unit (131) includes a flip flop (B0) by the delay circuit (P0) and a read register (RL). The input of delay circuit being applied as input (D) of the associated flip flop, whose output )Q) is applied on a corresponding input of the read register.

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