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    21.
    发明专利
    未知

    公开(公告)号：DE69732627D1

    公开(公告)日：2005-04-07

    申请号：DE69732627

    申请日：1997-09-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NAGARI ANGELO ,  NICOLLINI GERMANO

    IPC: H03M3/02 ,  H03M3/00

    Abstract: A second-order double-sampled analog/digital SIGMA DELTA converter uses two fully differential switched-capacitors integrators coupled in cascade; the first integrator has a fully-floating double-sampled, bilinear switched capacitor input structure, whereas the second integrator has a double-sampled linear switched-capacitor input structure, achieving an excellent SNR with a reduced number of switches for a low consumption.

    22.
    发明专利
    未知

    公开(公告)号：DE69430525T2

    公开(公告)日：2002-11-28

    申请号：DE69430525

    申请日：1994-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

    IPC: G06F1/24 ,  G11C7/22 ,  H03K3/356 ,  H03K17/00 ,  H03K17/22 ,  G11C7/00

    Abstract: An initialization circuit for memory registers (2), being of the type which comprises a signal input (I) being applied a supply voltage (Vp) which rises linearly from a null value, and an initializing output (O) connected to an input of a memory register (2) and on which a voltage signal (Vd) being equal or proportional to the supply voltage (Vp), during the initialization step, and a null voltage signal, upon the supply voltage (Vp) dropping below a predetermined tripping value (Vs), are produced, further comprises, between the input (I) and the output (O): a first circuit portion (3) connected to the input (I), a second circuit portion (4) connected after the first and having a first output (D) connected to the initializing output (O), and a third, inverting circuit portion (7) having an input connected to a second output (C) of the second portion (4) and an output (E) connected to the first portion to even hold off that first portion (3) while the supply voltage drops below the threshold voltage (Vs).

    23.
    发明专利
    未知

    公开(公告)号：DE69424668D1

    公开(公告)日：2000-06-29

    申请号：DE69424668

    申请日：1994-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO

    IPC: H01L27/04 ,  H01L21/822 ,  H02M3/07 ,  H02M3/00

    Abstract: An output voltage stabilisation circuit for a voltage multiplier of the type comprising a first charge transfer capacitor (C1) designed to take and transfer electrical charges from the input terminal (IN) to the output terminal (OUT) of a second capacitor (C2) for charge storage connected between the output terminal (OUT) and ground comprises an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage (Vrif) and the output voltage (Vout) of the voltage multiplier and said continuous voltage is applied to one terminal of said charge transfer capacitor (C1).

    24.
    发明专利
    未知

    公开(公告)号：DE69514523T2

    公开(公告)日：2000-06-15

    申请号：DE69514523

    申请日：1995-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO

    IPC: H02M3/07

    Abstract: A regulating circuit for the output voltage of a voltage booster, of the type which comprises a first charge transfer capacitor (C1) adapted to draw electric charges from the supply terminal (2) and transfer them to the output terminal (3), through electronic switches controlled by non-overlapped complementary phase signals, and a second charge storage capacitor (C2) connected between the output terminal (3) and ground (GND), further comprises an error amplifier which generates, during one of the operational phases, a DC voltage corresponding to the difference between a reference voltage (Vrif) and a voltage (Vx) being a duplicate of the output voltage (Vout) of the voltage booster; this DC voltage is applied directly to one end of the transfer capacitor (C1).

    25.
    发明专利
    未知

    公开(公告)号：DE69419897T2

    公开(公告)日：2000-05-31

    申请号：DE69419897

    申请日：1994-04-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  NAGARI ANGELO

    IPC: G11C27/02 ,  H03F3/00 ,  H03H19/00 ,  H03K5/24

    Abstract: A switched capacitor circuit (1) comprising an operational amplifier (OA), having first and second input terminals and an output terminal, the first input terminal being connected to a first reference potential, said operational amplifier (OA) being provided with a negative feedback network including a first capacitive element (C1) which is connected between the second input terminal and the output terminal of the operational amplifier, a second capacitive element (C2) which has a first terminal alternately connected to the second input terminal of the operational amplifier (OA) and to a reference potential, and a second terminal connected to a first circuit node (A) which is alternately connected to a signal input terminal (VIN) and said first output terminal (VOUT) of the operational amplifier (OA), the circuit (1) further comprising a third capacitive element (CX) connected between said circuit node (A) and a reference potential.

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