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公开(公告)号:JPH0865124A
公开(公告)日:1996-03-08
申请号:JP19462395
申请日:1995-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor: CONFALONIERI PIERANGELO , NICOLLINI GERMANO
IPC: H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K17/687
Abstract: PROBLEM TO BE SOLVED: To provide an electronic switch with which no body effect occur by suitably connecting the substrate of complementary transistor to the maximum and minimum potential references of integrated circuit(IC). SOLUTION: Between connecting terminals A and B, the source and drain of 1st and 2nd P channel transistors M1 and M2 are serially inserted. A transistor M3 composed of (n) channels is connected to the node of M1 and M2 and between them, a minimum electric reference Vss of IC having the electronic switch is inserted. Besides, a transistor M4 composed of (n) channels is inserted between the terminals A and B of M1 and M2 through source and drain terminals, and the substrates of M1 and M2 are connected to the terminals A and B. The substrates of M3 and M4 are connected to the reference Vss as well and M4 is driven by the inverse of ϕ signal through a gate terminal but M1 and M2 are driven by an opposite signal ϕ. The inverse of ϕsignal is impressed to M3, which can be driven by the signal ϕthrough the terminals of M1 and M2 and inverters, and this reference is defined as a maximum voltage reference.
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公开(公告)号:JPH0856144A
公开(公告)日:1996-02-27
申请号:JP13085995
申请日:1995-05-29
Applicant: ST MICROELECTRONICS SRL
Inventor: CONFALONIERI PIERANGELO , NICOLLINI GERMANO
Abstract: PURPOSE: To avoid the waste of power by setting the voltage of a circuit node B to be a zero value at the same time of setting the voltage of a circuit node A to be a supply power source voltage so as to make power consumption close to zero in a normal state. CONSTITUTION: When a supply power source voltage Vp is boosted, the voltage Va of the circuit node A is boosted to a value equal to the threshold value voltage Vt of a transistor(Tr)MN1 by time t2 . As resistance R1 is extremely high, at the additional and small boost of voltage δN, the node A is stabilized by the voltage value of Vn =Vt +δN. TrMP1 is maintained to be off until voltage between the voltage Vp and a gate terminal G3 reaches the conductive threshold value V of P-channel Tr. Though the boost of voltage δP at this point of time is small, negative impedance is added to the P-channel of TrMP1 to boost the voltage of the node B to the same value as Vp . Consequently, until the voltage Vp reaches a tripping threshold value VS, a voltage at the node B is zero In addition, as the result that a zero voltage value exists at the circuit node of a circuit part 4 at t1 , the voltage Vp exists on the gate terminal G2 of TrMN 2, voltage drop between a drain terminal D2 and the ground GND can be neglected.
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公开(公告)号:JPH06216733A
公开(公告)日:1994-08-05
申请号:JP23338493
申请日:1993-09-20
Applicant: ST MICROELECTRONICS SRL
Inventor: TOMASINI LUCIANO , CASTELLO RINALDO , CONFALONIERI PIERANGELO
IPC: H03K17/06 , H03K17/687
Abstract: PURPOSE: To unnecessitate activation time until reaching an ordinary state by setting the clock cycle of output terminal at the maximum power voltage value from the beginning by composing a driver circuit for electronic switch of an input pin for impressing a clock signal and a voltage duplexer connected between this pin and a switch. CONSTITUTION: In this driver circuit 1 for an electronic switch 2, the switch 2 is operated corresponding to the clock signal at a prescribed frequency. The switch 2 is composed of an N channel MOS transistor M3, its gate terminal is connected to an output terminal 0 of circuit 1 and its drain terminal and source terminal are functioned as switch terminals. The circuit 1 is provided with a pair of FET M1 and M2, and their drain terminals D1 and D2 are also connected to the terminal 0 together. When operating the circuit 1 in such configuration, a phase F at an input pin B is made high, the phase F at a pin A is made low, in such a state, the gate/source voltage drop of transistor M1 is made equal with a power supply voltage Vdd, the M2 is not conducted and a capacitor C is turned into charged state.
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公开(公告)号:JPH0898512A
公开(公告)日:1996-04-12
申请号:JP22351895
申请日:1995-08-31
Applicant: ST MICROELECTRONICS SRL
Inventor: NICOLLINI GERMANO , CONFALONIERI PIERANGELO
IPC: H01L27/04 , H01L21/822 , H02M3/07
Abstract: PROBLEM TO BE SOLVED: To stably maintain an output voltage and practically independent of a power supply voltage, a temperature, a process and within a certain limit, a load absorption current. SOLUTION: In an output voltage stabilization circuit which is composed of an input terminal IN, an output terminal OUT, a charge transmission capacitor C1 which takes out charges from the input terminal IN and transmits the charge to the output terminal OUT and an integrator, whose input is connected to the output terminal of a voltage multiplier and which generates a continuous voltage, corresponding to the difference between a reference voltage Vrif and the output voltage Vout of the voltage multiplier, the continuous voltage is supplied to one of the terminals of a charge transmission capacitor C1.
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公开(公告)号:JPH0715980A
公开(公告)日:1995-01-17
申请号:JP16278994
申请日:1994-06-21
Applicant: ST MICROELECTRONICS SRL
Inventor: NICOLLINI GERMANO , CONFALONIERI PIERANGELO , CRIPPA CARLO
Abstract: PURPOSE: To provide a voltage multiplier circuit of a stable output voltage, capable of practically taking out a relatively high output current which is in dependent of the respective kinds of parameters. CONSTITUTION: Error signals which are the displays of the differences between a reference voltage VRIF and an output voltage Vsur are generated, and the error signals are used for driving a transistor which acts as a switch for grounding a charge transfer capacitance C1 . Thus, the output voltage Vsur of this voltage multiplier is maintained fixed.
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公开(公告)号:JPH11154846A
公开(公告)日:1999-06-08
申请号:JP23985798
申请日:1998-08-26
Applicant: ST MICROELECTRONICS SRL
Inventor: NICOLLINI GERMANO , CONFALONIERI PIERANGELO
Abstract: PROBLEM TO BE SOLVED: To relatively easily manufacture with high reliability at competitive cost by arranging a second capacitor which is feedback connected and a pair of additional resistors which are feedback connected between an output and an inverted input of an operational amplifier. SOLUTION: A first resistor R1 is connected in parallel to a 1st capacitor C1 and in a second resistor R2 , one end is connected toa common node of the resistor R1 and the capacitor C1 , and the other end is connected to an inverted input of an operational amplifier 3. A second capacitor C2 is connected between an output V0 of the amplifier 3 and the inverted input, and two resistors R3 A and R3 B are connected in parallel to the capacitor C2 . A current IDAC enters directly into a common node of the resistors R3 A and R3 B. The transfer function of this filter does not change, even in the case of this restructured filter that has a current input of (IDAC). Consequently, it is possible to obtain a restructured filter which has high area efficiency for a power driven digital-analog converter.
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公开(公告)号:JPH0855964A
公开(公告)日:1996-02-27
申请号:JP11484195
申请日:1995-05-12
Applicant: ST MICROELECTRONICS SRL
Inventor: CONFALONIERI PIERANGELO
IPC: H01L27/04 , G06F11/00 , G11C5/00 , G11C7/10 , H01L21/82 , H01L21/822 , H01L27/07 , H03K19/173
Abstract: PURPOSE: To provide a device for selecting design option in an integrated circuit, with which any control signal is not required, an extremely small area is occupied, power consumption is practically zero and infinite formation is enabled on the same integrated circuit. CONSTITUTION: A correspondent circuit unit 12 of the integrated circuit 10 can adopt one of two possible different operative states so that any one of two design options for the integrated circuit can be selected. This device comprises an inverter 16, an output terminal 17 of that inverter is connected to a control terminal 13 of the circuit unit 12, and an input terminal 18 is connected through conductor A and B, which can be broken by means outside the integrated circuit, to a 1st power feeding terminal Vdd and to the 2nd power feeding terminal by a capacitor C1 parallel with a diode D1 connected for reverse conduction.
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公开(公告)号:JP2642901B2
公开(公告)日:1997-08-20
申请号:JP11484195
申请日:1995-05-12
Applicant: ST MICROELECTRONICS SRL
Inventor: CONFALONIERI PIERANGELO
IPC: H01L27/04 , G06F11/00 , G11C5/00 , G11C7/10 , H01L21/82 , H01L21/822 , H01L27/07 , H03K19/173
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公开(公告)号:JPH0888551A
公开(公告)日:1996-04-02
申请号:JP4035295
申请日:1995-02-28
Applicant: ST MICROELECTRONICS SRL
Inventor: NICOLLINI GERMANO , CONFALONIERI PIERANGELO
IPC: H03K17/16 , H03K17/687
Abstract: PURPOSE: To enable satisfactory open/close operation in a simple structure by inserting 1st and 2nd circuit elements between two connecting terminals, and inserting a 3rd circuit element between a node between these circuit elements and a voltage reference point. CONSTITUTION: During a phase signal ϕ1 for closing a switch, two circuit elements SW1 and SW2 operate just as one passage transistor(Tr) exists. When opening the switch, a node C is connected to a voltage reference point VCM by conducting a circuit element SW3 according to a signal ϕ2 . When a node A is a high impedance node, a current lower than a threshold value flowing through the Tr of SW2 is forced to flow into the voltage reference point. The SW3 forcedly connects the node C to the reference potential point, surely reduces the gate-source voltage of a complementary Tr at the SW1 lower than a threshold voltage and completely insulates the node A.
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公开(公告)号:JPH07142949A
公开(公告)日:1995-06-02
申请号:JP11291294
申请日:1994-05-26
Applicant: ST MICROELECTRONICS SRL
Inventor: DALLAVALLE CARLO , CRIPPA CARLO , CONFALONIERI PIERANGELO
Abstract: PURPOSE: To obtain the digital control circuit for amplifier gain control with low power consumption at a low cost. CONSTITUTION: The control circuit includes a peak detector 2 and a gain control stage 3 connected to an input terminal of a reception channel 1 via a coded signal rectifier circuit. The gain control stage includes a digital comparator 6 and two input terminals are connected respectively to the peak detector and an output terminal of a memory 8. The output terminal of the gain control stage 3 is connected to a gain control terminal of the amplifier stage FA. The content of addresses selectable in the memory 8 includes a prescribed peak level in a coded form.
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