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公开(公告)号：JPH0846488A
公开(公告)日：1996-02-16
申请号：JP9729995
申请日：1995-04-21
Applicant: ST MICROELECTRONICS SRL
Inventor： NICOLLINI GERMANO , NAGARI ANGELO
Abstract: PURPOSE: To provide a switching capacitor circuit lowering harmonic wave distortion without considerably increasing the complexity of circuit and the area required for integration as an integrated circuit. CONSTITUTION: This circuit has one operational amplifier (OA) 2 at least having 1st and 2nd input terminals at least and a 1st output terminal at least and connecting the 1st input terminal to a 1st reference potential and at this switching capacitor circuit provided with one negative feedback network at least provided with a capacitor C2 at the OA2 while having the 2nd input terminal through a switch SW1, the 1st terminal alternately connected to the 1st reference potential and the 2nd terminal connected through a switch SW2 alternately to a circuit node A connected to the 1st input and output terminals of OA2, a capacitor CX is provided at least while being connected between the circuit node A and a 2nd reference potential.
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2.发明专利
公开(公告)号：JPH11145838A
公开(公告)日：1999-05-28
申请号：JP25285098
申请日：1998-09-07
Applicant: ST MICROELECTRONICS SRL
Inventor： NAGARI ANGELO , NICOLLINI GERMANO
IPC: H03M3/02
Abstract: PROBLEM TO BE SOLVED: To provide an improved secondary order double sample type analog/ digital (A/D) ΣΔ converter. SOLUTION: This secondary order double sample type A/D ΣΔconverter uses two pieces of cascade, connected to completely differential switched capacitor integrators. The first integrator has a completely floating double sample type semi-double switched capacitor input component, and the second integrator has a double sample type primary switched capacitor input component on the other hand, with superior SNR, capable of decreasing the number of switches and lowering the power consumption.
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公开(公告)号：JPH08130422A
公开(公告)日：1996-05-21
申请号：JP18343495
申请日：1995-06-26
Applicant: ST MICROELECTRONICS SRL
Inventor： CASTELLO RINALDO , BASCHIROTTO ANDREA , NAGARI ANGELO
Abstract: PURPOSE: To eliminate the loss of a charge and to hold a dynamic characteristic by stitching the output of the input switched operational amplifier structure of a switched capacitance circuit to supply voltage. CONSTITUTION: The output of the input switched operational amplifier structure of the switched capacitance circuit is switched to supply voltage Vdd instead of making it to a ground value. It is realized by using a private integrated P-channel switch in a substrate connected to supply voltage Vdd and what is called body effect is removed. Thus, the output node of the input operational amplifier A1 does not take negative voltage during an operation when the switched operational amplifier is turned off. For subtracting Vdd/2 voltage instead of adding them, a clock phase for driving two switches S2 and S3 connecting a bias capacitor Cdc to the supply node and ground is exchanged. Thus, the arbitrary loss through respective substrates can be prevented.
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公开(公告)号：DE69621615D1
公开(公告)日：2002-07-11
申请号：DE69621615
申请日：1996-10-11
Applicant: ST MICROELECTRONICS SRL
Inventor： BASCHIROTTO ANDREA , NAGARI ANGELO , CASTELLO RINALDO
Abstract: In a switched operational amplifier including a differential input stage and at least a second output stage the compensation capacitor (CC) commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with switching means (M5P, M5N) controlled by the same control phase (Ph1) that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.
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5.发明专利
公开(公告)号：IT1392309B1
公开(公告)日：2012-02-24
申请号：ITRM20080664
申请日：2008-12-15
Applicant: ST MICROELECTRONICS SRL
Inventor： NICOLLINI GERMANO , NAGARI ANGELO
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Patent Agency Ranking
公开(公告)号：DE60205909T2
公开(公告)日：2006-06-08
申请号：DE60205909
申请日：2002-06-13
Applicant: ST MICROELECTRONICS SRL
Inventor： CONFALONIERI PIERANGELO , ZAMPROGNO MARCO , NAGARI ANGELO
Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.
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公开(公告)号：DE69723073D1
公开(公告)日：2003-07-31
申请号：DE69723073
申请日：1997-09-19
Applicant: ST MICROELECTRONICS SRL
Inventor： NAGARI ANGELO , NICOLLINI GERMANO
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公开(公告)号：DE69915251D1
公开(公告)日：2004-04-08
申请号：DE69915251
申请日：1999-03-24
Applicant: ST MICROELECTRONICS SRL
Inventor： CONFALONIERI PIERANGELO , NAGARI ANGELO , MECCHIA ALESSANDRO
Abstract: A set (Array_SAR) of sampling capacitors weighted according to a binary code is charged through a first capacitive unit (Array_Vin), whose capacitance is equal to the sum of the capacitances of the set (Array_SAR), at a voltage Vcm-Vin/2. The conversion is carried out by the SAR process by means of a comparator (13') and a logic unit (14') which operates the switches (SW1'-SW6') associated with the capacitors. The final position of the switches is loaded into a register (15') which supplies the digital output signal (Nout). To prevent any disturbances in the power supply and reference potential sources from affecting the accuracy of the conversion, two further capacitive units (Array_-Vref) and (Array_GND) are provided, with the same capacitance as the first capacitive unit, and these make it possible to present all the disturbances at the input of the comparator (13') in common mode and therefore without any effect on the output (OutCmp).
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公开(公告)号：ITRM20010407A1
公开(公告)日：2003-01-10
申请号：ITRM20010407
申请日：2001-07-10
Applicant: ST MICROELECTRONICS SRL
Inventor： CONFALONIERI PIERANGELO , ZAMPROGNO MARCO , NAGARI ANGELO
Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.
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公开(公告)号：DE69623963D1
公开(公告)日：2002-10-31
申请号：DE69623963
申请日：1996-10-11
Applicant: ST MICROELECTRONICS SRL
Inventor： BASCHIROTTO ANDREA , NAGARI ANGELO , CASTELLO RINALDO
Abstract: In switch-capacitor systems for extremely low supply voltage, employing fully differential switched op-amp, proper functioning of nMOS switches coupled to the inverting input node of an integrated stage capable of outputting a common mode control signal, is may possible by retaining the ground potential on the input node to prevent body effects on the threshold of nMOS switches by means of an auxiliary switched capacitor.
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