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    21.
    发明专利
    未知

    公开(公告)号：DE69421377D1

    公开(公告)日：1999-12-02

    申请号：DE69421377

    申请日：1994-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MANCUSO MASSIMO ,  POLUZZI RINALDO ,  RIZZOTTO GIANGUIDO

    IPC: H04N5/21 ,  G06T5/20 ,  H03H21/00 ,  H04N1/409

    Abstract: Filter achieving noise reduction and digital signal image edge exaltation comprising first and second noise reduction circuit means 2 and 3 designed to elect an image edge. Said first and second noise reduction circuit means 2 and 3 comprise each a first and second comparison element (S1,S2,S3,S4) whose input terminals are designed to receive separate digital signals of an image and an inferential circuit (C1,C2) connected to said comparison elements. Each inferential circuit (C1,C2) comprises a fuzzy logic unit designed to define activation levels (Vi) dependent upon signals generated by the comparison elements. The filter (1) comprises also a noise detection circuit (4) and an image edge detection circuit (6) both connected to the noise reduction circuit means (2,3) and designed to perform operations in accordance with fuzzy logic rules on the basis of activation levels (Vi) defined in the inferential circuits (C1,C2). The filter 1 also includes a noise reduction circuit (5) connected to the noise detection circuit (6) and designed to filter the digital image signals on the basis of the operations performed by the circuit (4). In the filter (1) is also included an image edge exalting circuit (7) connected to the noise reduction circuit (5) and to the image edge detection circuit (4) designed to perform on filtered digital image signals an image edge exaltation on the basis of the operations performed by the image edge detection circuit (6).

    24.
    发明专利
    未知

    公开(公告)号：DE602004016496D1

    公开(公告)日：2008-10-23

    申请号：DE602004016496

    申请日：2004-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MASCOLO DANILO ,  CEROFOLINI GIANFRANCO ,  RIZZOTTO GIANGUIDO

    IPC: B81C1/00 ,  G03F7/00 ,  H01L21/033

    Abstract: Method for realising a hosting structure of nanomettric elements (A, B) comprising the steps of depositing on an upper surface (12) of a substrate (10), of a first material, a block-seed (15) having at least one side wall (18). Depositing on at least one portion of sad surface (12) and on the block-seed (15) a first layer (20), of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it realising a spacer-seed (22) adjacent to the side wall (18). The method thus providing to repeat n times, with n >= 2, a step comprising a deposition on the substrate (10) of a layer (20, 30) of a predetermined material followed by a selective and anisotropic etching of the layer with realisation of at least one relative spacer (25, 35). This predetermined material being different for each pair of consecutive depositions. The above n steps defining at least one multilayer body (50, 150, 250). The method thus providing the step of selectively etching the multilayer body (50, 150, 250) removing a fraction of the spacers realising at least one plurality of nanometric hosting seats (40), the remaining fraction of the spacers realising contact terminals for a plurality of molecular transistors hosted in said hosting seats (40).

    25.
    发明专利
    未知

    公开(公告)号：DE60031401D1

    公开(公告)日：2006-11-30

    申请号：DE60031401

    申请日：2000-03-09

    Applicant: ST MICROELECTRONICS SRL ,  YAMAHA MOTOR EUROP

    Inventor： ULYANOV SERGUEI ,  RIZZOTTO GIANGUIDO ,  KURAWAKI ICHIRO ,  PANFILOV SERGUEI ,  GHISI FABIO ,  AMATO PAOLO ,  PORTO MASSIMO

    IPC: G05B13/02 ,  G06F17/30 ,  G06N99/00

    Abstract: A method of controlling a process driven by a control signal for producing a corresponding output includes producing an error signal as a function of a state of the process and of a reference signal. A control signal is generated as a function of the error signal and of a parameter adjustment signal. The control signal is applied to the process. A derived signal representative of a quantity to be minimized is calculated by processing paired values of the state of the process and the control signal. A correction signal is calculated from a set of several different values of the control signal that minimizes the derived signal. The parameter adjustment signal is calculated by a neural network and fuzzy logic processor from the error signal and the correction signal. The correction signal is periodically calculated by a Quantum Genetic Search Algorithm that results from a merging of a genetic algorithm and a quantum search algorithm.

    26.
    发明专利
    未知

    公开(公告)号：DE69930100T2

    公开(公告)日：2006-10-26

    申请号：DE69930100

    申请日：1999-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RIZZOTTO GIANGUIDO ,  CAPONETTO RICCARDO ,  DIAMANTE OLGA

    IPC: B60G17/015 ,  B60G23/00 ,  B60G17/018 ,  B60G21/10

    Abstract: A vehicle comprises at least one semiactive suspension (5) arranged between a vehicle body (2) and a wheel (4) and having a damping coefficient that can be varied in a controlled way by an actuator (14) governed by a control device (18). The control device comprises an accelerometric sensor (15) generating a vehicle body acceleration signal; a potentiometer (16) generating a suspension position signal; a signal conditioning unit (21) for the calculation of the vehicle body speed and the damping speed; a fuzzy control unit (23) which calculates the subsequent position of the actuator on the basis of the vehicle body speed and of the damping speed; and a driving unit (21) which generates a control signal (S1) for the actuator.

    27.
    发明专利
    未知

    公开(公告)号：DE602004001158D1

    公开(公告)日：2006-07-27

    申请号：DE602004001158

    申请日：2004-03-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KOCAREV LJUPCO ,  AMATO PAOLO ,  RIZZOTTO GIANGUIDO

    IPC: H04L9/00

    Abstract: An encryption process which is both secure and practical, does not require modular arithmetic, and therefore is very fast, and may be used for realizing a digital signature process, comprises the following steps: choosing preliminarily at least a private key and a set of permutable functions defined on a certain phase space for encrypting/decrypting messages, choosing a code for encoding messages to be sent in the form of a number belonging to the phase space, and wherein the set of permutable functions is composed of chaotic maps generated by a composite function of a first function, a second function and the inverse of the first function, the private key is defined by using the second function. It is possible to implement public-key encryption processes and related digital signature processes using chaotic maps by a computer program.

    28.
    发明专利
    未知

    公开(公告)号：DE69421377T2

    公开(公告)日：2000-03-23

    申请号：DE69421377

    申请日：1994-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MANCUSO MASSIMO ,  POLUZZI RINALDO ,  RIZZOTTO GIANGUIDO

    IPC: H04N5/21 ,  G06T5/20 ,  H03H21/00 ,  H04N1/409

    Abstract: Filter achieving noise reduction and digital signal image edge exaltation comprising first and second noise reduction circuit means 2 and 3 designed to elect an image edge. Said first and second noise reduction circuit means 2 and 3 comprise each a first and second comparison element (S1,S2,S3,S4) whose input terminals are designed to receive separate digital signals of an image and an inferential circuit (C1,C2) connected to said comparison elements. Each inferential circuit (C1,C2) comprises a fuzzy logic unit designed to define activation levels (Vi) dependent upon signals generated by the comparison elements. The filter (1) comprises also a noise detection circuit (4) and an image edge detection circuit (6) both connected to the noise reduction circuit means (2,3) and designed to perform operations in accordance with fuzzy logic rules on the basis of activation levels (Vi) defined in the inferential circuits (C1,C2). The filter 1 also includes a noise reduction circuit (5) connected to the noise detection circuit (6) and designed to filter the digital image signals on the basis of the operations performed by the circuit (4). In the filter (1) is also included an image edge exalting circuit (7) connected to the noise reduction circuit (5) and to the image edge detection circuit (4) designed to perform on filtered digital image signals an image edge exaltation on the basis of the operations performed by the image edge detection circuit (6).

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