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    TRENCHING METHOD
    1.
    发明专利
    TRENCHING METHOD 失效

    公开(公告)号：JPH1187491A

    公开(公告)日：1999-03-30

    申请号：JP18839898

    申请日：1998-07-03

    Applicant: ST MICROELECTRONICS SRL

    Inventor： QUEIROLO GIUSEPPE ,  OTTAVIANI GIAMPIERO ,  CEROFOLINI GIANFRANCO

    IPC: H01L21/302 ,  H01L21/265 ,  H01L21/301 ,  H01L21/304 ,  H01L21/306 ,  H01L21/76

    Abstract: PROBLEM TO BE SOLVED: To prevent an interlattice defect formed due to impact from being shifted by keeping the temperature of a crystalline target at a low level when ions are implanted at atomic weight and kinetic energy suitable for rendering the crystal amorphous up to a design depth within a range defined by an ion implantation mask. SOLUTION: When a crystal is a single crystal silicon substrate, the substrate is kept at -196 deg.C (boiling point of nitrogen), for example, and ions are implanted accurately up to a design depth corresponding to the kinetic energy of accelerating ion. Consequently, a crystal matrix is rendered amorphous through the majority shift mechanism of atom in a crystal lattice to be implanted. Since low temperature is kept in order to prevent diffusion of point defect occurring in a solid due to impact, the implanted ions are prevented from being diffused into an adjacent crystal lattice. Consequently, a spatial distribution of templanted ions characteristic of an isolation step face occurring simultaneously on both the side wall and the bottom face at an amorphous part can be attained.

    SEMICONDUCTOR INTEGRATED ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明专利
    SEMICONDUCTOR INTEGRATED ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：JP2003133551A

    公开(公告)日：2003-05-09

    申请号：JP2002203102

    申请日：2002-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CEROFOLINI GIANFRANCO ,  FERLA GIUSEPPE

    IPC: H01L21/8247 ,  H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L51/00

    Abstract: PROBLEM TO BE SOLVED: To provide a hybrid structure in which organic molecules are bonded with conventional silicon-based microelectronic structure to function as carriers of charged particles. SOLUTION: This MOS transistor structure contains a dielectric oxide layer (3) formed between two silicon plates (1, 2), wherein the silicon plates (1, 2) extend outside the circumference of the oxide layer (3), forming an undercut (5) having a substantially rectangular cross section. The surfaces of the silicon plates (1, 2) are chemically changed to form functional groups (6, 7) that are different from those on the surfaces in the remaining part outside the undercut (5) portion. Organic molecules (8) each having a reversible reduction center and having a molecular length substantially the same as the width of the undercut (5), are selectively reacted with the functional groups (6, 7) on the undercut (5) to form a covalent bond at each end of the organic molecules.

    5.
    发明专利
    未知

    公开(公告)号：DE69733471D1

    公开(公告)日：2005-07-14

    申请号：DE69733471

    申请日：1997-07-03

    Applicant: ST MICROELECTRONICS SRL

    Inventor： QUEIROLO GIUSEPPE ,  OTTAVIANI GIAMPIERO ,  CEROFOLINI GIANFRANCO

    IPC: H01L21/302 ,  H01L21/265 ,  H01L21/301 ,  H01L21/304 ,  H01L21/306 ,  H01L21/76

    Abstract: A process for cutting a trench in a silicon monocrystal in areas defined by a mask comprises forming a mask that defines the etch area on the surface of a monocrystallin silicon wafer eventually covered by a thin layer of oxide; implanting ions with a kinetic energy and in a dose sufficient to amorphize the silicon down to a predefined depth within the defined area, while maintaining the temperature of the wafer sufficiently low to prevent relaxation of point defects produced in the silicon and diffusion of the implanted ions in the crystal lattice of the silicon adjacent to the amorphized region; and heating the implanted wafer causing dislodgment and expulsion of the amorphized portion in correspondence of the interface with the adjacent crystal lattice of the silicon.

    6.
    发明专利
    未知

    公开(公告)号：DE69705387D1

    公开(公告)日：2001-08-02

    申请号：DE69705387

    申请日：1997-04-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CEROFOLINI GIANFRANCO ,  DE SANTI GIORGIO ,  CRISENZA GIUSEPPE

    IPC: C01B33/12 ,  C08F292/00 ,  C08L51/10 ,  H01B3/30 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is composed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

    8.
    发明专利
    未知

    公开(公告)号：DE602004016496D1

    公开(公告)日：2008-10-23

    申请号：DE602004016496

    申请日：2004-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MASCOLO DANILO ,  CEROFOLINI GIANFRANCO ,  RIZZOTTO GIANGUIDO

    IPC: B81C1/00 ,  G03F7/00 ,  H01L21/033

    Abstract: Method for realising a hosting structure of nanomettric elements (A, B) comprising the steps of depositing on an upper surface (12) of a substrate (10), of a first material, a block-seed (15) having at least one side wall (18). Depositing on at least one portion of sad surface (12) and on the block-seed (15) a first layer (20), of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it realising a spacer-seed (22) adjacent to the side wall (18). The method thus providing to repeat n times, with n >= 2, a step comprising a deposition on the substrate (10) of a layer (20, 30) of a predetermined material followed by a selective and anisotropic etching of the layer with realisation of at least one relative spacer (25, 35). This predetermined material being different for each pair of consecutive depositions. The above n steps defining at least one multilayer body (50, 150, 250). The method thus providing the step of selectively etching the multilayer body (50, 150, 250) removing a fraction of the spacers realising at least one plurality of nanometric hosting seats (40), the remaining fraction of the spacers realising contact terminals for a plurality of molecular transistors hosted in said hosting seats (40).

    9.
    发明专利
    未知

    公开(公告)号：DE69705387T2

    公开(公告)日：2001-10-11

    申请号：DE69705387

    申请日：1997-04-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CEROFOLINI GIANFRANCO ,  DE SANTI GIORGIO ,  CRISENZA GIUSEPPE

    IPC: C01B33/12 ,  C08F292/00 ,  C08L51/10 ,  H01B3/30 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is composed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

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