公开(公告)号：IT9020728D0

公开(公告)日：1990-06-22

申请号：IT2072890

申请日：1990-06-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  VAI GIANFRANCO ,  ZUFFADA MAURIZIO ,  BETTI GIORGIO

IPC: H03K19/0175 ,  H03K19/094 ,  H03K19/0948

Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).