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公开(公告)号：JPH0865064A
公开(公告)日：1996-03-08
申请号：JP19561095
申请日：1995-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , ALINI ROBERTO , CASTELLO RINALDO , VAI GIANFRANCO
Abstract: PROBLEM TO BE SOLVED: To control the gain of integrator with built-in transconductor by changing the output resistance of active load. SOLUTION: This device comprises a transconductance stage 3 having two input terminals I1 and I2 at least and two output terminals O1 and O2 at least and provided with an active load 4 connected to the output terminals O1 and O2 on the transconductance stage 3 and control circuit 5 for active load 4 connected between the output terminals O1 and O2 and the active load 4.
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公开(公告)号：JPH04273537A
公开(公告)日：1992-09-29
申请号：JP27297291
申请日：1991-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: PURPOSE: To obtain a finite state machine that is used for a highly reliable computing/adjustment system. CONSTITUTION: A combination logic 10 connected to a state memory 11 via the connections which transmit a future state signal 12 and a present state signal 13 is included. The logic 10 includes an input terminal 14 for the external input signals of a finite state machine and also an output terminal 15 for the output signals produced by the logic 10 itself. The finite state machine includes a comparison means 17 which compares at least one reference level 16 with the signal 12. Then the means 17 sets an error signal 18 to a means that resets the finite state machine and/or an adjustment system.
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公开(公告)号：JPH04239218A
公开(公告)日：1992-08-27
申请号：JP15065091
申请日：1991-06-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948
Abstract: PURPOSE: To provide a tri-state output gate structure capable of reducing active inputs and removing or substantially reducing the series connection of plural P-channel transistors(TRs) and allowed to be easily integrated by a CMOS integrated circuit. CONSTITUTION: The structure includes an active terminal 30 for receiving an active signal and an input terminal 31 for receiving an input signal and the input terminal 31 connects an output terminal 32 to a positive power supply terminal or a negative power supply terminal through a signal switching means 38. The active terminal 30 can be electrically connected to the gate terminal of a 1st P-channel TR 33 and the gate terminal of a 2nd N-channel TR 34 through signal inversion means 35, 37. The output terminal 32 is electrically connected to the drain terminals of the 1st and 2nd TRs 33, 34. The 1st and 2nd TRs 33, 34 electrically insulate the output terminal 32 from the input terminal 31.
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公开(公告)号：JPH03220913A
公开(公告)日：1991-09-30
申请号：JP30281290
申请日：1990-11-09
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/2897 , H03K3/0233
Abstract: PURPOSE: To reduce dependency against the inclination of the input signal waveform of an output change by providing a second differential cell having one input connected to output and the other input connected to a control circuit part provided with respective outputs connected to threshold input. CONSTITUTION: A transistor T9 is provided with a base B9 which is directly connected to an output terminal OUT as input for a second differential cell 9 and a collector C9 connected to a power electrode Vc. In the other transistor T10, the base B10 is connected to ground via a current power as second input and is connected to the emitter E11 of an npn-type transistor T14. T14 is connected to become diode constitution in the device 1, and the collector C14 is directly connected to the emitter E15 of the transistor T15. Threshold input S is connected to the collector C10 of the transistor T10 in the cell 9 and a comparator 1 is provided with the circuit part 10 effective for controlling a voltage value Vs appearing on threshold input S. Thus, dependency against the inclination of the input signal waveform of the output change can be reduced.
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公开(公告)号：EP0427016B1
公开(公告)日：1997-12-29
申请号：EP90119873
申请日：1990-10-17
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/2897 , H03K3/0233 , H03K3/023
CPC classification number: H03K3/02337
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Patent Agency Ranking
公开(公告)号：DE69129727D1
公开(公告)日：1998-08-13
申请号：DE69129727
申请日：1991-10-16
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
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公开(公告)号：IT1236692B
公开(公告)日：1993-03-26
申请号：IT2233589
申请日：1989-11-10
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/0233 , H03K3/2897 , H03F
Abstract: An electronic comparator device (1) with hysteresis, being of a type which comprises a differential cell (2) having a signal input (IN), an output (OUT), and a threshold input (S), further comprises a second differential cell (9) having one input (B9) connected to said output (OUT) and the other input (B10) connected to a controlling circuit portion (10) which has an output (E11) connected to the threshold input (S) to reduce the threshold voltage value (Vs) stepwise on the first change-over of the output (OUT) of the comparator (1).
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公开(公告)号：DE69614248D1
公开(公告)日：2001-09-06
申请号：DE69614248
申请日：1996-05-31
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： PISATI VALERIO , ALINI ROBERTO , COSENTINO GAETANO , VAI GIANFRANCO
Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2). In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).
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公开(公告)号：DE69519663T2
公开(公告)日：2001-04-26
申请号：DE69519663
申请日：1995-03-07
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , VAI GIANFRANCO , PORTALURI SALVATORE , DEMICHELI MARCO
Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics exploits the same digital/analog converter (DAC) that is normally used for controlling the time constant of the low pass loop filter for controlling the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground that introduces a third pole in the loop's transfer function. In this way the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant, thus the dumping factor remains constant while the omega o of the PLL is varied.
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公开(公告)号：DE69128987T2
公开(公告)日：1998-06-18
申请号：DE69128987
申请日：1991-06-17
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948
Abstract: The tristate output gate structure particularly for CMOS integrated circuits comprises an enable terminal (30) receiving an enable signal and an input terminal (31) receiving an input signal, which connects, through signal switching means (38), an output terminal (32) to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor (33) through signal inverting means (35,37) and to the gate terminal of a second N-channel transistor (34). The output terminal (32) is electrically connected to the drain terminals of the first and second transistors (33,34). The first and second transistors (33,34) electrically insulate the output terminal (32) from the input terminal (31).
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