-
公开(公告)号：JPH0831122A
公开(公告)日：1996-02-02
申请号：JP12230495
申请日：1995-05-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: PURPOSE: To obtain a servo signal processing device which is effectively used by a parallel structure PRML reading apparatus. CONSTITUTION: This device is used in a parallel structure PRML reading apparatus comprising a variable-gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23 and a couple of individual parallel processing channels 24, 34 sandwiched between the transversal analog filter 23 and RLL-NRZ decoder 25. Two processing channels 24, 34 are respectively provided with analog-digital converters 26, 36 and subsequent viterbi detectors 27, 37 and are operated depending on alternate sampling systems. The servo signal processing device 30 is provided with a rectifier 31 and an integrator 32 connected to the analog digital converters 26, 36.
-
公开(公告)号：JPH0773140A
公开(公告)日：1995-03-17
申请号：JP5280994
申请日：1994-02-25
Applicant: ST MICROELECTRONICS SRL
Inventor： ALINI ROBERTO , MOLONEY DAVID , GORNATI SILVANO , PORTALURI SALVATORE
Abstract: PURPOSE: To reduce the integration area and to accelerate the processing concerning a structure provided with a serial type interface for connection to a data transmission line, by connecting a part of a register to the bundled line and transmitting both a register address and data. CONSTITUTION: A decoded address latch 5 stores the output state of an address decoder 4 until the other address is transmitted through a multiplex bus 2. Only when this address is the address of a designated data register 1, according to the output of this latch 5, data transmitted after this address are written in this register. A write line 9 transmits a data write signal through a logic gate 7 of AND type. A data read circuit means 3 reads data out of this register 1 so as to repeat data from the multiplex bus 2. Only when the transmitted address is as prescribed, a read command starts reading from this register 1.
-
公开(公告)号：JPH07320404A
公开(公告)日：1995-12-08
申请号：JP11572495
申请日：1995-05-15
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , ALINI ROBERTO
Abstract: PURPOSE: To obtain a partial response signal (PRML) device by maximum likelihood sequence detection displaying no conventional fault. CONSTITUTION: This device has a variable gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23, and two separate parallel sampling channels 24, 34 inserted between the transversal analog filter 23 and a finite run length-non-return-to-zero type decoder 25. These sampling channels 24, 34 have analog-digital converters 26, 36 operated in accordance with sampling sequences, in which these each sampling channel is continued mutually and alternated mutually, and Viterbi detectors 27, 37.
-
公开(公告)号：JPH07182791A
公开(公告)日：1995-07-21
申请号：JP30156994
申请日：1994-11-10
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , DEMICHELI MARCO , ALINI ROBERTO
Abstract: PURPOSE: To facilitate the decoder of an operation mode by programming one of the output stream of the single bit of decoded data and the dual bit output stream of the decoded data. CONSTITUTION: The second re-timed output signals of a flip-flop B are supplied to the other input 1 of a MUX OUT multiplexer and the input of a forth flip- flop BB and the signals are sampled as the flip-flop AA by a second fractional clock frequency VCO/3. In this case, by performing different selection between the two inputs of an output multiplexers and selecting the one input, a single bit decoding NRZ stream becomes utilizable in the output of this decoder.
-
公开(公告)号：JPH0855436A
公开(公告)日：1996-02-27
申请号：JP32378294
申请日：1994-11-30
Applicant: ST MICROELECTRONICS SRL
Inventor： GADDUCCI PAOLO , MOLONEY DAVID , BETTI GIORGIO
Abstract: PURPOSE: To provide a survival sequence register of a simple structure having high reliability, by receiving a stream of logical sum of serial input streams SWP and SWN from G1, causing a first shift register F7 -F14 to remove spurious components, and causing a control circuit to generate an erase signal. CONSTITUTION: A survival sequence register is supplied with inputs of coded digital signals SWP, SWN corresponding to positive/negative certification peaks from a pickup and a clock signal CLK, and includes a variable threshold qualification circuit. The survival sequence register receives a logical sum output of SWP, SWN from an OR circuit G1 and removes spurious components by a shift register made of flip-flops F7 -F14 . A control circuit generates an erase signal. A second pointer shift register shifts through F7 -F14 and points out logic '1' of a sequence preceding logic '1' corresponding to a detection peak of the same code corresponding to the preceding logic '1'. With this structure, an SSR for variable threshold certification for channel recording having a simple structure and high reliability may be provided.
-
Patent Agency Ranking
公开(公告)号：JPH07176138A
公开(公告)日：1995-07-14
申请号：JP25471694
申请日：1994-09-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , BETTI GIORGIO , ALINI ROBERTO
Abstract: PURPOSE: To prevent the generation of errors by the transmission delay of signals by storing bits finally processed in a second combinational logic network (RC1) in a shift register, predicting the time when (n) bits are process in a first RC1 and synthesizing the signals in a second RC2. CONSTITUTION: The first RC1 processes the Q output tap (6:0) value of an FF for forming the shift register SR prior to the processing by the second RC2 of the corresponding bit for the complete two cycles of a synchronous block signal VCO. In order to secure the utilization of the entire cycle of the clock signal VCO which is a corresponding decoding value ND1 in the input D of the output register (FF) of a decoding NRZ output stream, a frequency which is partial compared to the base synchronous clock signal VCO in front of the rising front of a first clock signal and matched with the bit number ratio of input and output streams is provided. The bit finally processed in the RC2 is tentatively stored in the shift registers Q1-Q7, the time when the (n) bits are processed in the RC1 is predicted and the signals are synthesized in the RC2.
-
公开(公告)号：JPH07115355A
公开(公告)日：1995-05-02
申请号：JP24706894
申请日：1994-09-14
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , GADDUCCI PAOLO , MOLONEY DAVID
IPC: H03F1/30 , H03F3/45 , H03K5/1536 , H03K17/13 , H03K17/60
Abstract: PURPOSE: To eliminate the equivalent input offset of a comparator stage by cyclically inverting the connection of the input terminal of a comparator for supplying input signals after a detected zero cross. CONSTITUTION: After detecting that the zero cross is generated, comparison is performed with a minimum interval between the optional continuous two times of the zero crosses of the input signals S1 and an output state taken by the comparator G1 for practically small preliminarily set time is stored. This circuit is realized by using a deviater D for switching the input connection of the comparator G1 for supplying output signals S2 to the clock input terminal CK of a flip-flop for storing the output state. The flip-flop is sensitive to the unidirectional transition of clock signals S2 and the deviater D is driven by signals S7 delayed for a preliminarily set time interval by a delay circuit.
-
公开(公告)号：JP2642902B2
公开(公告)日：1997-08-20
申请号：JP12230495
申请日：1995-05-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
-
公开(公告)号：JPH06326536A
公开(公告)日：1994-11-25
申请号：JP9365394
申请日：1994-04-06
Applicant: ST MICROELECTRONICS SRL
Inventor： BETTI GIORGIO , MOLONEY DAVID , PORTALURI SALVATORE
Abstract: PURPOSE: To provide a variable gain amplifier provided with high dynamic characteristics and a wide frequency band, operated by a low voltage combining output signals which are generated by first and second amplifiers and a variable current oscillator and converting them by a converter. CONSTITUTION: This variable gain amplifier VGA is composed of a first voltage- current (V/I) amplifier, provided with a fixed gain and a second V/I amplifier provided with a variable gain operated in parallel with a first amplifier. Then, the output currents of the first and second amplifiers are totaled in a circuit for totaling and third current signals generated by the variable current oscillator driven by a control voltage VCONTROL are totaled as well. Then, the circuit Σfor totaling is used among three circuit blocks and a current-voltage converter (I/V) and supplies a low impedance node for totaling the output currents. Thus, the I/V converter converts the total of the output current signals of the three blocks into voltage signals.
-
公开(公告)号：JPH04273537A
公开(公告)日：1992-09-29
申请号：JP27297291
申请日：1991-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: PURPOSE: To obtain a finite state machine that is used for a highly reliable computing/adjustment system. CONSTITUTION: A combination logic 10 connected to a state memory 11 via the connections which transmit a future state signal 12 and a present state signal 13 is included. The logic 10 includes an input terminal 14 for the external input signals of a finite state machine and also an output terminal 15 for the output signals produced by the logic 10 itself. The finite state machine includes a comparison means 17 which compares at least one reference level 16 with the signal 12. Then the means 17 sets an error signal 18 to a means that resets the finite state machine and/or an adjustment system.
-
-
-
-
-
-
-
-
-
Search Results
34
records
(took 0.028 seconds)
