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公开(公告)号：JPH04233586A
公开(公告)日：1992-08-21
申请号：JP18060891
申请日：1991-06-26
Applicant: ST MICROELECTRONICS SRL
Inventor： GORNATI SILVANO , MERLO MAURO , ZUFFADA MAURIZIO , LIETAR LOIC
Abstract: PURPOSE: To provide an automatic device with wide operation band for varying the horizontal deflection frequency of the multi-synchronizing monitor. CONSTITUTION: This device includes an integrated circuit (2) wherein a frequency measuring circuit (3) to which an analog synchronizing signal (S1) is inputted at one input, a phase comparing circuit (14) which has two inputs (15 and 16) and to which the synchronizing signal (S1) is inputted at one input (15), a voltage-controlled oscillation circuit (12) which has a frequency depending upon an input voltage (Vc) and outputs a signal (S3) interlocking with the output (22) of the phase comparing circuit (14), and a counter (9) which has one input connected to the output (11) of the voltage-controlled oscillation circuit (12) and the other circuit connected to the output of the frequency measuring circuit (3), and also has its output (21) connected to the other input (16) of the phase comparing circuit (14) and outputted as the output signal of the integrated circuit (2) are incorporated.
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公开(公告)号：JPH07320404A
公开(公告)日：1995-12-08
申请号：JP11572495
申请日：1995-05-15
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , ALINI ROBERTO
Abstract: PURPOSE: To obtain a partial response signal (PRML) device by maximum likelihood sequence detection displaying no conventional fault. CONSTITUTION: This device has a variable gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23, and two separate parallel sampling channels 24, 34 inserted between the transversal analog filter 23 and a finite run length-non-return-to-zero type decoder 25. These sampling channels 24, 34 have analog-digital converters 26, 36 operated in accordance with sampling sequences, in which these each sampling channel is continued mutually and alternated mutually, and Viterbi detectors 27, 37.
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公开(公告)号：JP2003198274A
公开(公告)日：2003-07-11
申请号：JP2002234488
申请日：2002-08-12
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , BETTI GIORGIO , CHRAPPAN SOLDAVINI FRANCESCO , HASSNER MARTIN AURELIANO
Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a nonlinear passive element. SOLUTION: The circuit refers to nonlinear electronic equipment, especially in a nonlinear capacitor, more specifically, to the electronic circuit device that can be integrated on a semiconductor substrate (not limited). A nonlinear device is advantageously set to be a capacitor consisting of the feedback loop of a plurality of active blocks (2, 5, and 6), that are mutually subjected to cascade connection. Further, the invention can be integrated with or can be used relating to a network including other pieces of nonlinear device. COPYRIGHT: (C)2003,JPO
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公开(公告)号：JP2003142988A
公开(公告)日：2003-05-16
申请号：JP2002234482
申请日：2002-08-12
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , BETTI GIORGIO , CHRAPPAN SOLDAVINI FRANCESCO , HASSNER MARTIN AURELIANO
IPC: H01L21/822 , H01L27/04 , H03H11/48
Abstract: PROBLEM TO BE SOLVED: To easily integrate an electronic circuit having a non-linear passive element. SOLUTION: The invention relates to a non-linear electronic device and, more particularly, to a non-linear inductor. More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a inductor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.
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公开(公告)号：JPH0831122A
公开(公告)日：1996-02-02
申请号：JP12230495
申请日：1995-05-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: PURPOSE: To obtain a servo signal processing device which is effectively used by a parallel structure PRML reading apparatus. CONSTITUTION: This device is used in a parallel structure PRML reading apparatus comprising a variable-gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23 and a couple of individual parallel processing channels 24, 34 sandwiched between the transversal analog filter 23 and RLL-NRZ decoder 25. Two processing channels 24, 34 are respectively provided with analog-digital converters 26, 36 and subsequent viterbi detectors 27, 37 and are operated depending on alternate sampling systems. The servo signal processing device 30 is provided with a rectifier 31 and an integrator 32 connected to the analog digital converters 26, 36.
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Patent Agency Ranking
公开(公告)号：JP2642902B2
公开(公告)日：1997-08-20
申请号：JP12230495
申请日：1995-05-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
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公开(公告)号：JPH04273537A
公开(公告)日：1992-09-29
申请号：JP27297291
申请日：1991-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: PURPOSE: To obtain a finite state machine that is used for a highly reliable computing/adjustment system. CONSTITUTION: A combination logic 10 connected to a state memory 11 via the connections which transmit a future state signal 12 and a present state signal 13 is included. The logic 10 includes an input terminal 14 for the external input signals of a finite state machine and also an output terminal 15 for the output signals produced by the logic 10 itself. The finite state machine includes a comparison means 17 which compares at least one reference level 16 with the signal 12. Then the means 17 sets an error signal 18 to a means that resets the finite state machine and/or an adjustment system.
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公开(公告)号：JPH04239218A
公开(公告)日：1992-08-27
申请号：JP15065091
申请日：1991-06-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , VAI GIANFRANCO , ZUFFADA MAURIZIO , BETTI GIORGIO
IPC: H03K19/0175 , H03K19/094 , H03K19/0948
Abstract: PURPOSE: To provide a tri-state output gate structure capable of reducing active inputs and removing or substantially reducing the series connection of plural P-channel transistors(TRs) and allowed to be easily integrated by a CMOS integrated circuit. CONSTITUTION: The structure includes an active terminal 30 for receiving an active signal and an input terminal 31 for receiving an input signal and the input terminal 31 connects an output terminal 32 to a positive power supply terminal or a negative power supply terminal through a signal switching means 38. The active terminal 30 can be electrically connected to the gate terminal of a 1st P-channel TR 33 and the gate terminal of a 2nd N-channel TR 34 through signal inversion means 35, 37. The output terminal 32 is electrically connected to the drain terminals of the 1st and 2nd TRs 33, 34. The 1st and 2nd TRs 33, 34 electrically insulate the output terminal 32 from the input terminal 31.
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公开(公告)号：DE69129727D1
公开(公告)日：1998-08-13
申请号：DE69129727
申请日：1991-10-16
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
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公开(公告)号：DE69421071T2
公开(公告)日：2000-04-20
申请号：DE69421071
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , ALINI ROBERTO
Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.
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