公开(公告)号：EP0836268B1

公开(公告)日：2002-02-06

申请号：EP96830521.9

申请日：1996-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： Ghilardelli, Andrea ,  Mulatti, Jacopo ,  Ghezzi, Stefano

IPC: H02M3/07

CPC classification number: H02M3/073

公开(公告)号：EP0932202A1

公开(公告)日：1999-07-28

申请号：EP97830741.1

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Mulatti, Jacopo ,  Campardo, Giovanni ,  Maccarrone, Marco ,  Annunziata, Roberto

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0251

Abstract: The invention relates to an ESD protection network for a CMOS circuit structure integrated in a semiconductor substrate (2) and comprising discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply (Vcc) having a respective primary ground (GND), and from at least one secondary voltage supply (Vcc_IO) having a respective secondary ground (GND_IO). This network comprises essentially:

a first ESD protection element (15) for an input stage of the circuit structure;
a second ESD protection element (5) for an output stage of the circuit structure, the first (15) and second (5) protection elements having an input/output terminal (20) of the integrated circuit structure in common;
at least one ESD protection element (B0) between the primary supply (Vcc) and the primary ground (GND);
at least one ESD protection element (B) between the secondary supply (Vcc_IO) and the secondary ground (GND_IO).

Abstract translation: 本发明涉及一种用于集成在半导体衬底（2）中的CMOS电路结构的ESD保护网络，其包括形成在彼此电绝缘的各个衬底部分中的独立电路块，并且由至少一个初级电压源（Vcc ）具有相应的初级接地（GND），以及具有相应次级接地（GND_IO）的至少一个次级电压源（Vcc_IO）。 该网络基本上包括：用于电路结构的输入级的第一ESD保护元件（15） 用于所述电路结构的输出级的第二ESD保护元件（5），所述第一保护元件（15）和第二保护元件（5）具有所述集成电路结构的输入/输出端子（20）; 主电源（Vcc）和主接地（GND）之间的至少一个ESD保护元件（B0）; 在次级电源（Vcc_IO）和次级接地（GND_IO）之间的至少一个ESD保护元件（B）。