公开(公告)号：EP1403775B1

公开(公告)日：2006-03-08

申请号：EP02425576.2

申请日：2002-09-25

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Notarangelo, Giuseppe

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4213 ,  G06F13/4072

公开(公告)号：EP1403775A1

公开(公告)日：2004-03-31

申请号：EP02425576.2

申请日：2002-09-25

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Notarangelo, Giuseppe

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4213 ,  G06F13/4072

Abstract: Digital signals (D) are transmitted on a bus (P) at given instants (..., t-1, t, ...) selectively in a non-encoded format (D(t)) and an encoded format (NOT(D(t))) so as to minimize the switching activity (SA) on the bus. Given the same value of switching activity (12, 13), the decision whether to transmit the signals in non-encoded format or in encoded format is taken according to the choice of maintaining constant, without transitions, the value of the additional signal (INV), which signals that encoding of the signals transmitted each time has taken place or has been omitted.

Abstract translation: 该过程涉及在非编码和编码格式的验证条件复发哪个传输总线上在给定时刻给出的总线用于数字信号上相同的开关活性。 传输引起与所述信号相关联是反式mitted在另一个瞬间以保持其逻辑值相对于由用于preceding-即时附加信号假定逻辑值的附加信号。 因此独立权利要求中包括了以下内容：（1）编码器，用于以给定的时刻在总线上传输数字信号（2），用于在总线上接收数字信号的反式mitted一个解码器（3）的计算机程序产品可直接加载到的存储器 包括计算机和软件代码部分，用于执行数字信号发送过程。

公开(公告)号：EP1383042A1

公开(公告)日：2004-01-21

申请号：EP02425469.0

申请日：2002-07-19

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Pennisi, Agatino

IPC: G06F9/38

CPC classification number: G06F1/06 ,  G06F9/3869

Abstract: A pipeline structure (200) for use in a digital system (110) is proposed. The pipeline structure includes a plurality of stages (ST i ) arranged in a sequence from a first stage (ST 1 ) for receiving an input of the pipeline structure to a last stage (ST 5 ) for providing an output of the pipeline structure, at least one intermediate stage (ST 2 -ST 4 ) being interposed between the first stage and the last stage, wherein the first stage and the last stage are controlled by a main clock signal (CLK m ); the pipeline structure further includes phase shifting means (D 2 -D 4 ) for generating at least one local clock signal (CLK 2 -CLK 4 ) from the main clock signal for controlling the at least one intermediate stage, the main clock signal and the at least one local clock signal being out of phase.

Abstract translation: 提出了一种用于数字系统（110）的管线结构（200）。 流水线结构包括以从第一级（ST1）的顺序排列的用于接收流水线结构的输入到最后级（ST5）的多级（STi），用于提供流水线结构的输出，至少一个中间 （ST2-ST4）插入在第一级和最后级之间，其中第一级和最后级由主时钟信号（CLKm）控制; 所述流水线结构还包括用于从所述主时钟信号产生至少一个本地时钟信号（CLK2-CLK4）的相移装置（D2-D4），用于控制所述至少一个中间级，所述主时钟信号和所述至少一个本地 时钟信号异相。

公开(公告)号：EP1380961A1

公开(公告)日：2004-01-14

申请号：EP02425456.7

申请日：2002-07-10

Applicant: STMicroelectronics S.r.l.

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: G06F13/42

CPC classification number: G06F13/4239

Abstract: A process for transmitting data on a bus, minimizing the switching activity, involves converting the data between a first format (b(t)) and a second format (B(t)) used for transmission of the data. The conversion between said first format (b(t)) and said second format (B(t)) entails the swapping of position of respective bits within a cluster comprising a given number of bits, the swap operation being implementable according to different variants, the maximum number of said variants being equal to the factorial of the aforesaid given number. Each of said variants is identified by a respective pattern (P t ). Among the aforesaid patterns, an optimal pattern is selected which minimizes the switching activity (SA) at the moment of transmission of data on the bus. The data are then transmitted on the bus using the second format (B(t)) generated using said optimal pattern.

Abstract translation: 一种用于在总线上传送数据，使切换活动最小化的过程涉及在用于传输数据的第一格式（b（t））和第二格式（B（t））之间转换数据。 所述第一格式（b（t））和所述第二格式（B（t））之间的转换需要在包括给定位数的簇内的各个比特的位置的交换，所述交换操作可根据不同的变型实现， 所述变体的最大数量等于上述给定数量的阶乘。 每个所述变体由相应的图案（Pt）标识。 在上述模式中，选择在总线上传输数据时切换活动（SA）最小化的最佳模式。 然后使用使用所述最佳模式生成的第二格式（B（t））在总线上传送数据。

公开(公告)号：EP1124199A1

公开(公告)日：2001-08-16

申请号：EP00830082.4

申请日：2000-02-08

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Giacalone, Biagio ,  Palano, Carmelo

IPC: G06N7/04

CPC classification number: G06N7/04

Abstract: For encoded membership functions used to identify the atomic conditions defining the antecedents of fuzzy inferences, and also for the determination of the operands of the said antecedents, corresponding stores (6, 9) are configured for the storage of the already available values of these encoded membership functions and of the said operands. At the time of identification of a new value for the said quantities, a check is made (5, 7) to see whether this value is already present in the corresponding store (6, 9). If the outcome of this check is positive, in the case of encoded membership functions, the mechanism by which the encoded fuzzy inferences point to these functions is changed, so that the pointers of the encoded fuzzy inferences are redirected towards the membership functions which are already stored. In the case of the operands of the antecedents, the check of the corresponding back-up store (9) is carried out preferably on the basis of the corresponding calculation values, the calculation of a new operand being disabled when it is found that the corresponding calculation parameters are already present in the corresponding back-up store (9). The aforesaid store (9) is preferably configured as a stack to which new calculated operand values are written at the uppermost position, with the possibility of making values identified as already present shift back to this uppermost position.

Abstract translation: 对于用于识别限定模糊推理的前提的原子条件的编码的隶属函数，以及用于确定所述前提的操作数，对应的存储（6,9）被配置用于存储这些编码的已经可用的值 隶属函数和所述操作数。 在识别所述数量的新值时，进行检查（5,7）以查看该值是否已经存在于相应的存储器中（6,9）。 如果该检查的结果是肯定的，则在编码的隶属函数的情况下，编码的模糊推理指向这些函数的机制被改变，使得编码的模糊推理的指针被重定向到已经存在的隶属函数 存储。 在前提的操作数的情况下，最好根据对应的计算值对相应的备用存储（9）进行检查，当操作数的计算被发现为相应的 计算参数已经存在于相应的备用存储（9）中。 上述存储器（9）优选地被配置为在最上位置写入新的计算的操作数值的堆栈，使得被识别为已经存在的值可能返回到该最高位置的可能性。

公开(公告)号：EP1752872A3

公开(公告)日：2008-06-25

申请号：EP06116753.2

申请日：2006-07-06

Applicant: STMicroelectronics S.r.l.

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco

IPC: G06F7/74 ,  G06F7/485

CPC classification number: G06F7/74 ,  G06F7/485

Abstract: A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.

公开(公告)号：EP1439470B1

公开(公告)日：2007-07-25

申请号：EP03425013.4

申请日：2003-01-14

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Visalli, Giuseppe

IPC: G06F13/42

CPC classification number: G06F13/4286

公开(公告)号：EP1524810A1

公开(公告)日：2005-04-20

申请号：EP03425663.6

申请日：2003-10-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pappalardo, Francesco ,  Notarangelo, Giuseppe ,  Visalli, Giuseppe

IPC: H04L25/49 ,  H04B10/155

CPC classification number: H04B10/5055 ,  H04B10/503 ,  H04B10/516 ,  H04B10/801 ,  H04L25/4915

Abstract: In a method for transmitting on an optical connection (16) a sequence of input data (b(t)) comprising first ("1") and second ("0") logic states, there is envisaged the operation of providing an optical source (15) for generating an optical signal to be transmitted on said optical connection (16), said optical source (15) being able to generate optical pulses at the occurrence of said first ("1") logic states. The method comprises the operation of:
      - encoding (470,570) said sequence of input data (b(t)) in an encoded sequence of data (B(t)) prior to transmission on said optical connection (16), where said encoding operation minimizes the first logic states ("1") in said encoded sequence of data (B(t)).
A preferential application is to optical-fibre communication systems with on-chip integrated buses.

Abstract translation: 在用于在光学连接（16）上发送包括第一（“1”）和第二（“0”）逻辑状态的输入数据序列（b（t））的方法中，设想提供光源 （15），用于产生要在所述光学连接（16）上传输的光信号，所述光源（15）能够在出现所述第一（“1”）逻辑状态时产生光脉冲。 该方法包括以下操作： - 在所述光学连接（16）上传输之前，在编码的数据序列（B（t））中编码（470,570）所述输入数据序列（b（t）），其中所述编码操作 使所述编码数据序列（B（t））中的第一逻辑状态（“1”）最小化。 优先应用于具有片上集成总线的光纤通信系统。

公开(公告)号：EP1524772A1

公开(公告)日：2005-04-20

申请号：EP03425662.8

申请日：2003-10-13

Applicant: STMicroelectronics S.r.l.

Inventor： Visalli, Giuseppe ,  Pappalardo, Francesco ,  Avellone, Giuseppe ,  Rimi, Francesco ,  Galluzzo, Agostino

IPC: H03M13/25 ,  H04L27/233

CPC classification number: H04L1/0059 ,  H03M13/256 ,  H04L1/0054 ,  H04L1/0068 ,  H04L25/067 ,  H04L27/2272 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: A phase recovery and decoding method for decoding signals (S'(t)) comprising encoded symbols (u k ) over a respective symbol interval (T) which modulate a carrier, for example in a TCM system. The method envisages performing (20 to 26) a phase locking of the signal to be decoded so as to obtain a phase-locked signal which can present, during each symbol interval (T), variations induced by disturbances (noise, fading, etc.). The value attributed to the decoded symbol (U k ) is a function of the value assumed by the phase-locked signal on at least one subinterval of the symbol interval (T), for example located at the end of the symbol interval (T). Alternatively, the value assumed by the phase-locked signal on a plurality of subintervals comprised in each symbol interval (T) is detected (24,32), and a respective majority value of said phase-locked signal within said plurality of subintervals is identified (34,36). A suitable phase recovery and decoding circuit comprises a phase comparator (20), hard decision means (24), an encoder circuit (26), an oscillator (22) and a selection unit (28). For determining decoded value (U k ) and updating the state of the encoder circuit.

Abstract translation: 一种相位恢复和解码方法，用于在例如在TCM系统中调制载波的相应符号间隔（T）上对包括编码符号（uk）的信号（S'（t））进行解码。 该方法设想对待解码的信号执行（20至26）相位锁定，以获得在每个符号间隔（T）期间可能存在由干扰（噪声，衰落等）引起的变化的锁相信号。 ）。 归因于解码符号（Uk）的值是在符号间隔（T）的至少一个子间隔（例如位于符号间隔（T）的结尾）处由锁相信号假设的值的函数。 或者，检测包括在每个符号间隔（T）中的多个子间隔上的锁相信号所假设的值（24,32），并且识别所述多​​个子区间内的所述锁相信号的相应多数值 （34,36）。 合适的相位恢复和解码电路包括相位比较器（20），硬判决装置（24），编码器电路（26），振荡器（22）和选择单元（28）。 用于确定解码值（Uk）并更新编码器电路的状态。

公开(公告)号：EP1443669A1

公开(公告)日：2004-08-04

申请号：EP03425058.9

申请日：2003-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Rimi, Francesco ,  Avellone, Giuseppe ,  Pappalardo, Francesco ,  Speziali, Filippo ,  Galluzzo, Agostino

IPC: H04B1/707 ,  H04B7/26

CPC classification number: H04B1/70735 ,  H04B1/7083 ,  H04B1/709 ,  H04B2201/70707

Abstract: In a first step, slot synchronization is obtained by setting in correlation (210, 220) the received signal (r) with a primary sequence (SG), which represents the primary channel (PSC), and by storing said received signal. During a second step, the said correlator (210, 220) is re-used for correlating the received signal (r) with a secondary sequence (SSC) corresponding to the secondary synchronization codes. The correlator (210) is preferably structured in the form of a first filter (210) and of a second filter (220) set in series, which receive a first secondary sequence (SG1) and a second secondary sequence (SG2), typically consisting of Golay sequences. Proposed herein are architectures of a parallel and serial type, as well as architectures designed for re-using further circuit parts. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95, or WBCDMA.

Abstract translation: 在第一步骤中，通过将接收信号（r）与表示主信道（PSC）的主序列（SG）相关联（210,220）并存储所述接收信号来获得时隙同步。 在第二步骤期间，所述相关器（210,220）被重新用于使接收信号（r）与对应于辅同步码的辅助序列（SSC）相关。 相关器（210）优选地被构造成串联设置的第一滤波器（210）和第二滤波器（220）的形式，其接收第一次级序列（SG1）和第二次级序列（SG2），典型地由 Golay序列。 这里提出的是并行和串行类型的体系结构，以及为重新使用更多电路部分而设计的体系结构。 优先应用在基于诸如UMTS，CDMA2000，IS95或WBCDMA的标准的移动通信系统中。