公开(公告)号：EP1555760A1

公开(公告)日：2005-07-20

申请号：EP04290135.5

申请日：2004-01-19

Applicant: STMicroelectronics N.V. ,  STMicroelectronics S.r.l.

Inventor： Zory, Julien ,  Speziali, Filippo

IPC: H03M13/29 ,  H03M13/27

CPC classification number: H03M13/6566 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/3972

Abstract: A method and device for handling write access conflicts in interleaving, in particular for high-throughput turbo decoding for wireless communication systems; the device comprises N interleaving buffers (CLk) that are respectively connected to N producers (PRk), an LLR distributor means and N single port target memories (TMk). At any time step, each interleaving buffer receives m LLR inputs from the producers and has to write up to M of these into a register bank (RBk), which comprises W registers. M denotes the maximum number of concurrent write operations supported per time step and W denotes the maximum buffer size. M and W are design parameters and are chosen for the standard case and not for the worst case. m-M producers have to be stalled whenever m is larger than M and m producers have to be stalled whenever a buffer overflow occurs (more than W LLR values). Finally, at any time step one LLR value is fetched from the register bank and written to the SRAM interleaving memory.

Abstract translation: 一种用于处理交织中的写访问冲突的方法和装置，特别是用于无线通信系统的高吞吐量turbo解码; 该装置包括分别连接到N个生成器（PRk），LLR分配器装置和N个单端口目标存储器（TMk）的N个交织缓冲器（CLk）。 在任何时间步长中，每个交织缓冲器从生产者接收m个LLR输入，并且必须将这些M写入到包括W寄存器的寄存器组（RBk）中。 M表示每个时间步长支持的最大并发写操作数，W表示最大缓冲区大小。 M和W是设计参数，为标准情况选择，而不是最坏情况。 每当m大于M时，m-M生产者必须停顿，并且每当出现缓冲区溢出（多于W LLR值）时，生产者必须停止生产。 最后，在任何时候，从寄存器组中取出一个LLR值并将其写入SRAM交错存储器。

公开(公告)号：EP1555760B1

公开(公告)日：2008-05-28

申请号：EP04290135.5

申请日：2004-01-19

Applicant: STMicroelectronics N.V. ,  STMicroelectronics S.r.l.

Inventor： Zory, Julien ,  Speziali, Filippo

IPC: H03M13/29 ,  H03M13/27

CPC classification number: H03M13/6566 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/3972

公开(公告)号：EP1443669A1

公开(公告)日：2004-08-04

申请号：EP03425058.9

申请日：2003-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Rimi, Francesco ,  Avellone, Giuseppe ,  Pappalardo, Francesco ,  Speziali, Filippo ,  Galluzzo, Agostino

IPC: H04B1/707 ,  H04B7/26

CPC classification number: H04B1/70735 ,  H04B1/7083 ,  H04B1/709 ,  H04B2201/70707

Abstract: In a first step, slot synchronization is obtained by setting in correlation (210, 220) the received signal (r) with a primary sequence (SG), which represents the primary channel (PSC), and by storing said received signal. During a second step, the said correlator (210, 220) is re-used for correlating the received signal (r) with a secondary sequence (SSC) corresponding to the secondary synchronization codes. The correlator (210) is preferably structured in the form of a first filter (210) and of a second filter (220) set in series, which receive a first secondary sequence (SG1) and a second secondary sequence (SG2), typically consisting of Golay sequences. Proposed herein are architectures of a parallel and serial type, as well as architectures designed for re-using further circuit parts. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95, or WBCDMA.

Abstract translation: 在第一步骤中，通过将接收信号（r）与表示主信道（PSC）的主序列（SG）相关联（210,220）并存储所述接收信号来获得时隙同步。 在第二步骤期间，所述相关器（210,220）被重新用于使接收信号（r）与对应于辅同步码的辅助序列（SSC）相关。 相关器（210）优选地被构造成串联设置的第一滤波器（210）和第二滤波器（220）的形式，其接收第一次级序列（SG1）和第二次级序列（SG2），典型地由 Golay序列。 这里提出的是并行和串行类型的体系结构，以及为重新使用更多电路部分而设计的体系结构。 优先应用在基于诸如UMTS，CDMA2000，IS95或WBCDMA的标准的移动通信系统中。