公开(公告)号：EP1713083A1

公开(公告)日：2006-10-18

申请号：EP05425207.7

申请日：2005-04-11

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo

IPC: G11C16/16

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/24

Abstract: The invention relates to a non volatile memory electronic device (20) integrated on semiconductor and of the Flash EEPROM type with NAND architecture comprising at least one memory matrix (21) divided into physical sectors, intended as smallest erasable units, and organised in rows or word lines (WL) and columns or bit lines (BL) of memory cells.
At least one row (ROW_i) or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being completely erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line (SSL) of source line.

Abstract translation: 本发明涉及集成在半导体上的非易失性存储器电子器件（20）和具有NAND架构的闪存EEPROM类型的非易失性存储器电子器件（20），其包括至少一个被划分为物理扇区的存储器矩阵（21），其被设计为最小的可擦除单元， 字线（WL）和存储器单元的列或位线（BL）。 给定物理扇区的至少一行（ROW_i）或字线电连接到相邻物理扇区的至少一行或字线，以形成完全可擦除的单个逻辑扇区，其中相应单元的源终端 该对连接的行指的是源线的相同选择行（SSL）。

公开(公告)号：EP1363292A3

公开(公告)日：2004-07-21

申请号：EP03010684.3

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

IPC: G11C16/10 ,  G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

公开(公告)号：EP0798727B1

公开(公告)日：2004-05-26

申请号：EP96830162.2

申请日：1996-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C5/02 ,  G11C16/06

CPC classification number: G11C5/025 ,  G11C16/28

公开(公告)号：EP1381057A1

公开(公告)日：2004-01-14

申请号：EP02425453.4

申请日：2002-07-10

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C16/16 ,  G11C16/08 ,  G11C8/12

CPC classification number: G11C8/12 ,  G11C16/08 ,  G11C16/16

Abstract: A line selector for a matrix of memory elements, for example a word line selector, comprises a plurality of line group selection circuits (1031-103p,107,399), each one allowing the selection (PSS1-PSSp) of a respective group of matrix lines (WL1-WLk,...,WLq-WLm) according to an address (RADD1); each matrix line group includes at least one matrix line. Flag means (303) are associated with each line group, that can be set (307,LD-ER) to declare a pending status of a prescribed operation, for example an erase operation, for the respective matrix line group. Means ( 301,319 ) are provided for entrusting the flag means with the selection of the respective line group during the execution of the prescribed operation ( ER-P/VFY ), in alternative to the respective line group selection circuit. The flag means enable, when set, the execution of the prescribed operation on the respective matrix line group.

Abstract translation: 用于存储器元件矩阵（例如字线选择器）的线选择器包括多个线组选择电路（1031-103p，107,399），每个线组选择电路允许各组矩阵线的选择（PSS1-PSSp） （WL1-WLK，...，WLq-WLm）根据地址（RADD1）; 每个矩阵线组包括至少一个矩阵线。 标志装置（303）与可以被设置（307，LD-ER）的每个线路组相关联，以宣布针对各个矩阵线路组的规定操作（例如擦除操作）的等待状态。 提供装置（301,319），用于在执行规定的操作（ER-P / VFY）期间委托标志装置选择相应的行组，以替代相应的行组选择电路。 标志意味着在设置时启用对各矩阵线组的规定操作的执行。

公开(公告)号：EP1363292A2

公开(公告)日：2003-11-19

申请号：EP03010684.3

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

IPC: G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses.
Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract translation: 本发明涉及一种用于对多电平型非易失性存储器件进行编程的方法，包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。 该方法在不同的阈值下应用不同的漏极电压值。 这样的值与由各个存储器字位获得的阈值水平成正比，并且有效地提供在寻求方式中同时获得在有限数量的脉冲结束时的电平的电平 。 有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

公开(公告)号：EP0798742B1

公开(公告)日：2003-11-12

申请号：EP96830166.3

申请日：1996-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C16/06

CPC classification number: G11C7/12 ,  G11C16/08

公开(公告)号：EP1359591A1

公开(公告)日：2003-11-05

申请号：EP02425273.6

申请日：2002-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/3427 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/3418

Abstract: An NROM memory device, wherein the memory cells (1) are provided with charge storage regions (12) of insulating material, such as silicon nitride. The memory device includes a row decoder (50) comprising a plurality of drivers (53); during programming, a first driver supplies a first voltage (Vpp) having a first value to a selected wordline (WL), while the other drivers (53) are configured so as to supply a second voltage (Voff) having a second non-zero value, lower than the first value, to the other wordlines. Thereby, the gate-drain voltage drop of the deselected cells is reduced, and thus spurious erasing of the deselected cells connected to the selected bitline is reduced. Consequently, the reliability of the memory device is improved considerably and the life thereof is lengthened, thanks to the reduction in the charge injected into the charge storage region (12).

Abstract translation: NROM存储装置，worin存储器单元（1）被提供有绝缘材料，颜色的电荷存储区域（12）：如氮化硅。 所述存储器装置包括一个行解码器（50），其包括驱动器的多个（53）; 在编程期间，第一驱动器提供具有第一值到选择的字线（WL）的第一电压（Vpp）为，而另一个驱动器（53）被配置以提供具有第二非零的第二电压（V关闭） 值，比所述第一值低时，向其它字线。 由此，取消选择的单元的栅极 - 漏极电压降减小，并且连接到选定位线的取消选择的细胞。因此杂散擦除减小。 因此，存储器装置的可靠性显着提高，其寿命被延长，这要归功于在注入到电荷存储区域（12）的电荷的减少。

公开(公告)号：EP1293905A1

公开(公告)日：2003-03-19

申请号：EP01830591.2

申请日：2001-09-17

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0223 ,  G06F12/06

Abstract: A pointer circuit for pointing to elements in at least one collection of elements comprises a base pointer ( 105 ) adapted to provide a first binary code ( B_ADD ) defining a first address of an element in the collection. The pointer circuit also comprises a binary shift circuit ( 109 ) receiving the first binary code provided by the base pointer and a second binary code ( SK_VALa, SK_VALb ) defining a shift value. The binary shift circuit combines the first and second binary codes to provide a third binary code ( S_ADDa,S_ADDb ) defining a second address of an element in the collection differing from the first address by the shift value.

Abstract translation: 用于指向至少一个元素集合中的元素的指针电路包括适于提供定义集合中元素的第一地址的第一二进制码（B_ADD）的基指针（105）。 指针电路还包括接收由基准指针提供的第一二进制码的二进制移位电路（109）和定义移位值的第二二进制码（SK_VALa，SK_VALb）。 二进制移位电路组合第一和第二二进制代码以提供第三二进制代码（S_ADDa，S_ADDb），其定义与第一地址不同的移位值的集合中的元素的第二地址。

公开(公告)号：EP0788111B1

公开(公告)日：2002-11-13

申请号：EP96830047.5

申请日：1996-02-05

Applicant: STMicroelectronics S.r.l.

Inventor： Fontana, Marco ,  Pascucci, Luigi

IPC: G11C8/00

CPC classification number: G11C8/08

公开(公告)号：EP0802483B1

公开(公告)日：2002-01-30

申请号：EP96830217.4

申请日：1996-04-18

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi

IPC: G06F11/20

CPC classification number: G11C29/84