公开(公告)号：EP1365417A1

公开(公告)日：2003-11-26

申请号：EP02425293.4

申请日：2002-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

IPC: G11C16/10 ,  G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses.
Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract translation: 本发明涉及一种用于对多电平型非易失性存储器件进行编程的方法，包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。 该方法在不同的阈值下应用不同的漏极电压值。 这样的值与由各个存储器字位获得的阈值水平成正比，并且有效地提供在寻求方式中同时获得在有限数量的脉冲结束时的电平的电平 。 有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。

公开(公告)号：EP0997913B1

公开(公告)日：2005-08-10

申请号：EP98830654.4

申请日：1998-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Marco ,  Rolandi, Paolo ,  Montanaro, Massimo

IPC: G11C29/00 ,  G11C11/56 ,  G06F11/20

CPC classification number: G11C29/50 ,  G06F2201/81 ,  G11C11/56 ,  G11C11/5642 ,  G11C2029/5006 ,  G11C2211/5634

Abstract: A method for testing virgin memory cells in a multilevel memory device which comprises a plurality of memory cells, the particularity of which consists of the fact that it comprises the steps of: reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

公开(公告)号：EP1353371A1

公开(公告)日：2003-10-15

申请号：EP02425225.6

申请日：2002-04-12

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Marco

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/11266 ,  G11C11/5692 ,  H01L27/112

Abstract: A process for fabricating a two-bit ROM cell, comprises forming a control electrode ( 1052n,1053n ) over a semiconductor layer ( 103 ) of a first conductivity type, a region of the semiconductor layer underlying the control electrode constituting a memory cell channel region; and providing, on either side of the channel region, differentiated-resistance doped regions ( 1151-1154;2011-2014,2031-2034 ) having respective resistance values that depends on a logic state of a respective one of the two bits to be stored in the cell, the resistance values of the differentiated-resistance doped regions being set by means of a selective introduction of dopants. The differentiated-resistance doped regions are formed by selectively providing sidewall spacers ( 109 ) at sidewalls of the control electrode, and using the sidewall spacers as a mask against the introduction of dopants.

Abstract translation: 一种用于制造两比特ROM单元的方法，包括在第一导电类型的半导体层（103）上形成控制电极（1052n，1053n），构成存储单元通道区域的控制电极下面的半导体层的区域 ; 并且在沟道区域的任一侧上提供具有取决于要存储的两个位中的相应一个的逻辑状态的各自的电阻值的差分电阻掺杂区域（1151-1154; 2011-2014,2031-2034） 在电池中，通过选择性地引入掺杂剂来设定差分电阻掺杂区的电阻值。 差分电阻掺杂区域通过在控制电极的侧壁处选择性地提供侧壁间隔物（109）而形成，并且使用侧壁间隔物作为防止引入掺杂剂的掩模。

公开(公告)号：EP0997913A1

公开(公告)日：2000-05-03

申请号：EP98830654.4

申请日：1998-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Marco ,  Hollandi, Paolo ,  Montanaro, Massimo

IPC: G11C29/00 ,  G11C11/56 ,  G06F11/20

CPC classification number: G11C29/50 ,  G06F2201/81 ,  G11C11/56 ,  G11C11/5642 ,  G11C2029/5006 ,  G11C2211/5634

Abstract: A method for testing virgin memory cells in a multilevel memory device which comprises a plurality of memory cells, the particularity of which consists of the fact that it comprises the steps of:

reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not;
determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell;
the at least one reference memory cell being chosen with a gradually higher threshold;
when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

Abstract translation: 一种用于测试多层存储器件中的原始存储器单元的方法，其包括多个存储器单元，其特殊性包括以下事实：其包括以下步骤：读取构成存储器件的各个存储单元，并将 这些存储单元同时具有至少一个参考存储器单元，以便确定存储器单元的阈值是否低于至少一个参考存储器单元的阈值; 确定阈值高于所述至少一个参考小区的阈值的存储器单元的数量; 所述至少一个参考存储器单元被选择为具有逐渐更高的阈值; 当发现阈值高于给定参考阈值的存储单元的数量足够低于设置在存储装置中的冗余存储单元的数目时，假设给定参考阈值为存储器件的较低参考阈值，则确定 存储单元阈值的统计分布。

公开(公告)号：EP1363292A3

公开(公告)日：2004-07-21

申请号：EP03010684.3

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

IPC: G11C16/10 ,  G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses. Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

公开(公告)号：EP1363292A2

公开(公告)日：2003-11-19

申请号：EP03010684.3

申请日：2003-05-13

Applicant: STMicroelectronics S.r.l.

Inventor： Pascucci, Luigi ,  Rolandi, Paolo ,  Riva, Marco

IPC: G11C11/56

CPC classification number: G11C11/5628

Abstract: The invention relates to a method for programming a non-volatile memory device of the multi-level type, comprising a plurality of transistor cells grouped into memory words and conventionally provided with gate and drain terminals. The method applies different drain voltage values at different threshold values. Such values are directly proportional to the threshold levels to be attained by the individual memory word bits, and effective to provide for a simultaneous attainment of the levels, in a seeking-to manner, of the levels at the end of a limited number of pulses.
Advantageously, a constant gate voltage value is concurrently applied to the gate terminals of said cells, such that the cell programming time is unrelated to the threshold level sought.

Abstract translation: 本发明涉及一种用于对多电平型非易失性存储器件进行编程的方法，包括分组成存储字的多个晶体管单元，并且通常设置有栅极和漏极端子。 该方法在不同的阈值下应用不同的漏极电压值。 这样的值与由各个存储器字位获得的阈值水平成正比，并且有效地提供在寻求方式中同时获得在有限数量的脉冲结束时的电平的电平 。 有利地，恒定栅极电压值同时施加到所述单元的栅极端子，使得单元编程时间与所寻求的阈值水平无关。