公开(公告)号：EP0777319B1

公开(公告)日：2003-03-05

申请号：EP95830500.5

申请日：1995-11-30

Applicant: STMicroelectronics S.r.l.

Inventor： Tomasini, Luciano ,  Castello, Rinaldo ,  Clerici, Giancarlo ,  Bietti, Ivan

IPC: H03F1/00 ,  H03F1/08

CPC classification number: H03F1/086

公开(公告)号：EP0744829B1

公开(公告)日：2003-01-15

申请号：EP95830217.6

申请日：1995-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： Tomasini, Luciano ,  Castello, Rinaldo ,  Bietti, Ivan ,  Clerici, Giancarlo

IPC: H03H1/00 ,  H03F3/45

CPC classification number: H03F3/45475 ,  H03F3/45982 ,  H03F2203/45526

公开(公告)号：EP1094608A1

公开(公告)日：2001-04-25

申请号：EP99830657.5

申请日：1999-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Guinea, Jesus ,  Tomasini, Luciano ,  Maggio, Santo

IPC: H03L7/081 ,  H03L7/091

CPC classification number: H03L7/0812 ,  H03L7/091

Abstract: A delay-locked loop circuit ("DLL") comprises a delay line (1) with a delay (Δt) which can be varied in a controlled manner in order to delay a periodic input signal (CKin) of period T, and circuit means (2, 7) for controlling the delay line (1) in order to lock the delay (Δt) to the period T.
The delay line (1) supplies to the control circuit means (2, 7) a plurality of periodic signals (CK1-CKN) each delayed relative to the periodic input signal by a respective fraction of the delay (Δt), and the control circuit means (2, 7) comprise sequence-detector circuit means (2) which can periodically detect, in the delayed signals, characteristic sequences of digital values indicative of the delay (Δt) and, in dependence on the type of characteristic sequence, can bring about a reduction or an increase in the delay (Δt) for locking to the period T.

Abstract translation: 延迟锁定环电路（“DLL”）包括具有延迟（DELTA t）的延迟线（1），其可以以受控的方式变化，以便延迟周期T的周期性输入信号（CKin），并且电路 用于控制延迟线（1）以便将延迟（DELTA t）锁定到周期T的装置（2,7）。延迟线（1）向控制电路装置（2,7）供应多个周期 信号（CK1-CKN）各自相对于周期性输入信号延迟相应的延迟分数（DELTA t），并且控制电路装置（2,7）包括顺序检测器电路装置（2） 在延迟信号中，指示延迟（DELTA t）的数字值的特征序列和根据特征序列的类型可以导致锁定到周期T的延迟（DELTA t）的减小或增加 。

公开(公告)号：EP1091485A1

公开(公告)日：2001-04-11

申请号：EP99830632.8

申请日：1999-10-08

Applicant: STMicroelectronics S.r.l.

Inventor： Tomasini, Luciano ,  Guinea, Jesus

IPC: H03F3/30

CPC classification number: H03F3/3028 ,  H03F3/3023

Abstract: An input stage (315) for a buffer (300) with negative feedback, having an input terminal (310in), an output terminal (110int), a first (110v) and a second (110g) supply terminal, a biasing branch (Ipa-Ipb), a first (M1a-Mm1a) and a second (Mm1b-M1b) balancing branch each comprising an active transistor (M1a; M1b) for supplying, at the output terminal (110int), a current depending on the current difference in the first (M1a-Mm1a) and second (M1mb-M1b) balancing branches, the biasing branch (Ipa-Ipb) and the first (M1a-Mm1a) and second (Mm1b-M1b) balancing branches being connected in parallel between the first (110v) and second (110g) supply terminals, wherein the input terminal (310in) divides the biasing branch into two input branches (Ipa-Dina; Dinb-Ipb) each comprising a constant-current generator (Ipa; Ipb), each active transistor (M1a; M1b) being connected to a corresponding current generator (Ipa; Ipb) for receiving a control voltage (Vgs) correlated with a voltage at the terminals of the current generator (Ipa; Ipb).

Abstract translation: 具有负反馈的缓冲器（300）的输入级（315），具有输入端（310in），输出端（110int），第一（110v）和第二（110g）供电端，偏压分支 -Ipb），第一（M1a-Mm1a）和第二（Mm1b-M1b）平衡支路，每个支路包括有源晶体管（M1a; M1b），用于在输出端（110int）处提供取决于电流差 第一（M1a-Mm1a）和第二（M1mb-M1b）平衡分支，偏置分支（Ipa-Ipb）和第一（M1a-Mm1a）和第二（Mm1b-M1b）平衡分支并联连接在第一（ 110v）和第二（110g）电源端子，其中输入端子（310in）将偏置支路分成两个分别包括恒流发生器（Ipa; Ipb）的输入支路（Ipa-Dina; Dinb-Ipb），每个有源晶体管 （M1a; M1b）连接到相应的电流发生器（Ipa; Ipb），用于接收与端子上的电压相关的控制电压（Vgs） 当前发电机（Ipa; IPB）。

公开(公告)号：EP1075107A1

公开(公告)日：2001-02-07

申请号：EP99830518.9

申请日：1999-08-06

Applicant: STMicroelectronics S.r.l.

Inventor： Guinea, Jesus ,  Tomasini, Luciano

IPC: H04L7/033 ,  H03L7/081 ,  H03L7/07

CPC classification number: H04J3/0685 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A bidirectional synchronous interface for the reception of a first flow of digital data (RX, RXEQ) with a first coding from a communication channel (2a), and for the transmission on said communication channel (2b) of a second flow of digital data (TX) with said first coding in synchrony with a local timing signal (CK), comprises synchronization means (6, 8) for synchronizing the interface with the first flow of digital data (RX, RXEQ).
The synchronization means comprise first circuit means (8) fed by said local timing signal (CK) to generate, starting from said local timing signal (CK), a plurality of repetition timing signals (CK1-CKn) delayed from one another by fractions of a period, and second circuit means (6) fed by said first flow of digital data (RX, RXEQ) and by said plurality of repetition timing signals (CK1-CKn) suitable for determining, in said plurality, a pre-selected repetition timing signal (CKR) substantially in synchrony with the first flow of digital data (RX, RXEQ).

Abstract translation: 一种双向同步接口，用于接收来自通信信道（2a）的第一编码的第一数字数据流（RX，RXEQ），以及用于在所述通信信道（2b）上传输第二数字数据流（ TX）与本地定时信号（CK）同步地具有所述第一编码，包括用于使接口与第一数字数据流（RX，RXEQ）同步的同步装置（6,8）。 同步装置包括由本地定时信号（CK）馈送的第一电路装置（8），以从所述本地定时信号（CK）开始产生多个相互延迟的重复定时信号（CK1-CKn） 以及由所述第一数字数据流（RX，RXEQ）和所述多个重复定时信号（CK1-CKn）馈送的第二电路装置（6），所述多个重复定时信号适合于在所述多个中确定预先选择的重复定时 信号（CKR）基本上与第一数字数据流（RX，RXEQ）同步。

公开(公告)号：EP0579891B1

公开(公告)日：1999-03-31

申请号：EP92830401.3

申请日：1992-07-22

Applicant: STMicroelectronics S.r.l.

Inventor： Tomasini, Luciano ,  Castello, Rinaldo ,  Erratico, Pietro

IPC: H04M1/00 ,  H04M1/58 ,  H04B1/58

CPC classification number: H04M1/585 ,  H04B1/586 ,  H04M1/76

公开(公告)号：EP0587966B1

公开(公告)日：1999-02-10

申请号：EP92830498.9

申请日：1992-09-16

Applicant: STMicroelectronics S.r.l.

Inventor： Tomasini, Luciano ,  Castello, Rinaldo

IPC: H04M19/08

CPC classification number: H04M19/08

Abstract: A certain amount of DC supply current derivable from a subscriber's line (VL, GROUND) is used for powering at respective regulated voltages a plurality of functional circuits (A,B...) of an equipment connectable to the line. A sensible energy saving can be achieved by splitting the valuable current among the functional circuits, on account of their priority rank, by using at least a differential pair of current delivering transistors (P2,P3). A special circuit monitors the actual current of absorption of the functional circuit of highest rank (A) and produces a control signal that is used for modifying the drive conditions of the current delivering transistors. The current waste caused by sinking a design maximum current through a dissipative shunt voltage regulator of each functional circuit as done in the prior art circuits, is prevented and all the current exceeding the actual absorption needs of the highest rank functional circuit may be distributed to the other functional circuits without waste. This same principle may be advantageously applied also to functional circuits of lesser and lesser rank of priority for maximizing the saving.

Abstract translation: 可以从用户线路（VL，GROUND）导出的一定量的直流电源电流用于向各个调节电压供电可连接到线路的设备的多个功能电路（A，B ...）。 通过使用至少一个差分对的电流输送晶体管（P2，P3），通过分配功能电路中的有价值的电流，由于它们的优先等级可以实现明智的节能。 专用电路监控最高等级（A）的功能电路的实际吸收电流，并产生用于修改电流输送晶体管的驱动条件的控制信号。 通过在现有技术电路中通过每个功能电路的耗散分流电压调节器设计最大电流引起的当前浪费被防止，并且超过最高功能电路的实际吸收需要的所有电流可以分配到 其他功能电路无浪费。 这个相同的原理也可以有利地应用于功能电路的优先级越来越少，从而最大化节省。