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    Process for forming a buried cavity in a semiconductor material wafer
    1.
    发明公开
    Process for forming a buried cavity in a semiconductor material wafer 审中-公开
    Herstellungsverfahren eines vergrabenen Hohlraumes in einer Halbleiterscheibe

    公开(公告)号：EP1130631A1

    公开(公告)日：2001-09-05

    申请号：EP00830148.3

    申请日：2000-02-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Erratico, Pietro ,  Sacchi, Enrico ,  Villa, Flavio ,  Barlocchi, Gabriele ,  Corona, Pietro

    IPC: H01L21/308

    CPC classification number: B81C1/00404

    Abstract: The process comprises the steps of forming, on top of a semiconductor material wafer (10), a holed mask (16) having a lattice structure and comprising a plurality of openings (18) each having a substantially square shape and a side with an inclination of 45° with respect to the flat (110) of the wafer; carrying out an anisotropic etch in TMAH of the wafer (10), using said holed mask (16), thus forming a cavity (20), the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapour deposition (CVD) using TEOS, thus forming a TEOS layer (24) which completely closes the openings of the holed mask (16) and defines a diaphragm (26) overlying the cavity (20) and on which a suspended integrated structure can subsequently be manufactured.

    Abstract translation: 该方法包括以下步骤：在半导体材料晶片（10）的顶部上形成具有格子结构的孔掩模（16），并且包括多个开口（18），每个开口（18）均具有大致正方形的形状， 相对于晶片的平面（110）为45°; 使用所述带孔掩模（16）在晶片（10）的TMAH中进行各向异性蚀刻，从而形成空腔（20），其横截面具有倒立的等腰梯形的形状; 并使用TEOS进行化学气相沉积（CVD），由此形成TEOS层（24），该TEOS层完全封闭了孔罩（16）的开口，并且限定了覆盖空腔（20）的隔膜（26） 随后可以制造悬浮综合结构。

    Integrated semiconductor structure
    5.
    发明公开
    Integrated semiconductor structure 审中-公开
    Integrierte Halbleiterstruktur

    公开(公告)号：EP1172848A1

    公开(公告)日：2002-01-16

    申请号：EP00830492.5

    申请日：2000-07-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Erratico, Pietro

    IPC: H01L21/762 ,  H01L21/822 ,  H01L27/02

    CPC classification number: H01L29/7816 ,  H01L21/762 ,  H01L21/822 ,  H01L27/0248

    Abstract: Integrated structure 100 in a chip of semiconductor material comprising a substrate 101 having a first type of conductivity and an epitaxial layer 102 grown on said substrate and having a conductivity of the first type less than the conductivity of the substrate.
    Moreover, the integrated structure comprises a first region 104 and a second region 105 included in the epitaxial layer and having a conductivity opposite to that of the layer, said first and said second regions extending from a surface 103' of the epitaxial layer opposite the substrate into the layer so as to form a first and a second junction with said layer, and means for reducing an injection of current through the layer from said first to said second region when the first junction is directly biased. The integrated structure is characterized by the fact that said means comprise an isolating element 107 located between said first and second regions and extending from said surface of the epitaxial layer substantially at least as far as the substrate.

    Abstract translation: 包括半导体材料芯片的集成结构100，其包括具有第一类型的导电性的衬底101和在所述衬底上生长的导电性小于衬底的导电性的外延层102。 此外，集成结构包括包含在外延层中并且具有与层相反的导电性的第一区域104和第二区域105，所述第一和第二区域从与衬底相对的外延层的表面103'延伸 以形成与所述层的第一和第二结，以及用于当第一结被直接偏置时减少从所述第一区到第二区的电流注入的装置。 该集成结构的特征在于，所述装置包括位于所述第一和第二区域之间的隔离元件107，并且从所述外延层的所述表面基本上至少与基底一样远。

    MOS varactor, in particular for radio-frequency transceivers
    6.
    发明公开
    MOS varactor, in particular for radio-frequency transceivers 审中-公开
    MOS Varaktor，insbesonderefürRadiofrequenzsender-Empfänger

    公开(公告)号：EP1024538A1

    公开(公告)日：2000-08-02

    申请号：EP99830044.6

    申请日：1999-01-29

    Applicant: STMicroelectronics S.r.l.

    Inventor： Manzini, Stefano ,  Erratico, Pietro

    IPC: H01L29/94

    CPC classification number: H01L29/94

    Abstract: A varactor (30) has a gate region (6), a first and a second biasing region (5a, 5b) of N + type, embedded in a well (4), and a first and a second extraction region (15a, 15b) of P + type, forming a pair of PN junctions (16a, 16b) with the well (4). The PN junctions (16a, 16b) are inversely biased and extract charge accumulating in the well (4), below the gate region (6), when the gate region (6) is biased to a lower voltage (V G ) than a predetermined threshold value.

    Abstract translation: 变容二极管（30）具有栅极区域（6），N +型的第一和第二偏置区域（5a，5b），嵌入阱（4），以及第一和第二提取区域 ，15b），与阱（4）形成一对PN结（16a，16b）。 当栅极区域（6）被偏置到比预定阈值更低的电压（VG）时，PN结（16a，16b）被反向偏置并且提取电荷累积在阱（4）中，在栅极区域（6） 值。

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