公开(公告)号：EP0729228B1

公开(公告)日：2003-01-15

申请号：EP95830049.3

申请日：1995-02-22

Applicant: STMicroelectronics S.r.l.

Inventor： Alini, Roberto ,  Brianti, Francesco ,  Pisati, Valerio ,  Demicheli, Marco

IPC: H03H1/00 ,  H03H11/04 ,  H03H15/00

CPC classification number: H03H15/00 ,  H03H11/0422

公开(公告)号：EP0695030B1

公开(公告)日：2001-06-13

申请号：EP94830390.4

申请日：1994-07-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Alini, Roberto ,  Castello, Rinaldo ,  Vai, Gianfranco

IPC: H03G1/00 ,  H03F1/08 ,  H03H11/04

CPC classification number: H03F3/45883 ,  H03F3/45286 ,  H03F3/45807 ,  H03F2203/45648 ,  H03G1/0023

公开(公告)号：EP0948135A1

公开(公告)日：1999-10-06

申请号：EP98830191.7

申请日：1998-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Portaluri, Salvatore ,  Pisati, Valerio ,  Zangrandi, Luigi

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A device for generating pulses of high-precision programmable duration, whose particularity is the fact that it comprises:

-- first pulse generator means (1) which are suitable to receive in input a pulse generation command signal (IN) and to emit in output a first pulse for loading the contents of a register in counter means (2);
-- second pulse generator means (4), triggered by the first pulse in output from the first pulse generator means (1);
-- third pulse generator means (6), triggered by a second pulse emitted by the second pulse generator means and suitable to generate a third pulse to restart the second pulse generator means;
the second pulse emitted by the second pulse generator means (4) constituting a clock signal for the counter means (2) in order to produce a decrement in the counter means; the signal in output from the counter means (2) being the pulsed signal to be generated (OUT); the duration of the pulsed signal being determined by the content of the counter means (2).

Abstract translation: 一种用于产生高精度可编程持续时间的脉冲的装置，其特点在于其包括： - 第一脉冲发生器装置（1），其适于在输入端接收脉冲发生命令信号（IN）并发射输出 用于在计数器装置（2）中加载寄存器的内容的第一脉冲; - 第二脉冲发生器装置（4），由第一脉冲发生器装置（1）输出的第一脉冲触发; - 第三脉冲发生器装置（6），由第二脉冲发生器装置发射的第二脉冲触发并适于产生第三脉冲以重启第二脉冲发生器装置; 由第二脉冲发生器装置发出的第二脉冲构成计数器装置（2）的时钟信号，以产生计数器装置的减量; 来自计数器装置（2）的输出中的信号是要产生的脉冲信号（OUT）; 脉冲信号的持续时间由计数器装置（2）的内容确定。

公开(公告)号：EP0948132A1

公开(公告)日：1999-10-06

申请号：EP98830192.5

申请日：1998-03-31

Applicant: STMicroelectronics S.r.l.

Inventor： Marchese, Stafano ,  Pisati, Valerio ,  Portaluri, Salvatore ,  Savo, Alessandro

IPC: H03G3/00 ,  H03G1/00 ,  H03G7/00

CPC classification number: H03G7/06 ,  H03G1/0023

Abstract: An amplifier with programmable gain and input linearity, comprising an input stage (10), which is suitable to receive a voltage signal (V + , V - ) and perform current conversion thereof with compression, and an output stage (30), which is connected to the input stage (10) and is suitable to decompress the signal in output from the input stage, producing gain amplification thereof; the particularity of the amplifier is the fact that it further comprises at least one current amplifier stage (20) which is interposed between the input stage (10) and the output stage (30) and comprises at least one bipolar transistor (21, 22) which is series-connected to a load diode (23, 24) and to a current source (2I 2 ); programmable means (I 2 , I 2 *) for reducing the transconductance of the load diode (23, 24) being provided in the at least one amplifier stage (20) to determine a programmable amplification factor for the gain of the amplifier.

Abstract translation: 具有可编程的增益和输入线性放大器，所有这些是适合于接收包括输入级的电压信号（10），（V <+> V < - >），并用其压缩进行电流转换，并且到输出级（30 ），所有这些是连接到输入级（10）和适用于从输入级输出到解压缩信号，产生它们的增益放大; 放大器的特殊性是它还包括factthat该输入级（10）和输出级（30）之间并且包括至少一个双极性晶体管（21，22）的至少一个电流放大器级（20）的所有 所有这一切都被串联连接到负载二极管（23，24）和电流源（2I2）; 可编程装置（I2，I2 *）用于减小负载二极管（23，24）在所述至少一个放大级（20）设置的跨导到确定性矿可编程放大因子用于放大器的增益。

公开(公告)号：EP0794609A1

公开(公告)日：1997-09-10

申请号：EP96830103.6

申请日：1996-03-08

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Demicheli, Marco ,  Pisati, Valerio

IPC: H03B1/00 ,  H03L7/099

CPC classification number: H03L7/0805 ,  H03L7/099

Abstract: The system described comprises various circuit units (10, 11, 12) each having a capacitor (C0, C1, C2) and charging means (G0, G1, G2) for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors.
In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop (PLL) which uses one (10) of the circuit units as an adjustable oscillator, and current transducer means (17) which regulate the charging currents of the capacitors (C1, C2) of the circuit units (11, 12) in dependence on the regulated charging current of the capacitor (C0) of the oscillator (10) or the error current of the PLL loop.

Abstract translation: 所描述的系统包括各种电路单元（10，11，12），每个具有一个电容器（C0，C1，C2）和用于在所述之间的比率（I / C）定义的量DEPENDING充电装置（G0，G1，G2） 充电电流和电容器的电容。 为了由于在集成电路制造工艺的参数的波动自动为从标称电容的实际电容的偏差进行补偿，该系统具有电路单元的锁相环（PLL），其使用（10）之一 作为可调振荡器，和电流传感器装置（17）从而调节电容器的电路单元的充电电流（C1，C2）（11，12）在根据所述振荡器的电容器的调节充电电流（C0） （10）或者PLL环路的误差电流。

公开(公告)号：EP0810723A1

公开(公告)日：1997-12-03

申请号：EP96830311.5

申请日：1996-05-31

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME.

Inventor： Pisati, Valerio ,  Alini, Roberto ,  Cosentino, Gaetano ,  Vai, Gianfranco

IPC: H03H1/00 ,  H03F3/45 ,  H03F3/72

CPC classification number: H03F3/72 ,  H03F3/45286 ,  H03F2203/45302 ,  H03F2203/45304 ,  H03F2203/45371 ,  H03F2203/45396 ,  H03F2203/45506

Abstract: A BiCMOS Transconductor differential stage (10) for high frequency filters comprises an input circuit portion having signal inputs (IN+,IN-) and comprising a pair of MOS transistors (M1,M2) having their respective gate terminals (G1,G2) corresponding to the signal inputs as well as an output circuit portion having signal outputs (OUT-,OUT+) and comprising a pair of two-pole transistors (Q1,Q2) connected together with a common base in a circuit node (B) and inserted between inputs (IN+,IN-) and outputs (OUT-,OUT+) in cascode configuration. The stage (10) in accordance with the present invention calls for a switching device (3) associated with at least one of said added two-pole transistors (Q1,Q2) to change the connections between the parasite capacitors present in the transconductor stage. The switching device (3) also comprises at least one added two-pole transistor (Q1x, Q2x) connected in a removable manner in parallel with the corresponding two-pole cascode transistor (Q1,Q2).
In a variant embodiment there are also provided respective added MOS transistors (M1x,M2x) connected in parallel with the MOS transistors (M1,M2) of the input portion to change the ratio W:L of each of the input transistors (M1,M2).

Abstract translation: 一种用于高频滤波器的BiCMOS跨导差分级（10）包括具有信号输入端（IN +，IN-）并包括一对MOS晶体管（M1，M2）的输入电路部分，所述一对MOS晶体管的各自的栅极端子（G1，G2） 信号输入端以及具有信号输出端（OUT-，OUT +）的输出电路部分，并且包括在电路节点（B）中用公共基极连接在一起的一对双极晶体管（Q1，Q2），并插入在输入端 （IN +，IN-）和输出（OUT-，OUT +）级联配置。 根据本发明的级（10）需要与所述增加的双极晶体管（Q1，Q2）中的至少一个相关联的开关器件（3）改变跨导级中存在的寄生电容器之间的连接。 开关器件（3）还包括至少一个与对应的双极共源共栅晶体管（Q1，Q2）并联连接的增加的双极晶体管（Q1x，Q2x）。 在变型实施例中，还提供了与输入部分的MOS晶体管（M1，M2）并联连接的相应增加的MOS晶体管（M1x，M2x），以改变每个输入晶体管（M1，M2）的比率W:L ）。

公开(公告)号：EP0786858A1

公开(公告)日：1997-07-30

申请号：EP96830035.0

申请日：1996-01-26

Applicant: SGS-THOMSON MICROELECTRONICS s.r.l. ,  CO.RI.M.ME. CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO

Inventor： Alini, Roberto ,  Bruccoleri, Melchiorre ,  Cosentino, Gaetano ,  Pisati, Valerio

IPC: H03F1/00 ,  H03F3/30

CPC classification number: H03F3/3077

Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage.
The amplifier has a very low or zero offset ( Vos = Vout-Vin ).

Abstract translation: 所描述的放大器具有由推挽装置中的npn晶体管（Q1）和pnp晶体管（Q2）和驱动器级构成的输出级。 后者包括电流镜电路，其在其输入支路中具有与第一恒定电流发生器（G1）串联的pnp晶体管（Q3），并且在其输出支路中具有npn晶体管（Q4）和两个互补的 集电极一起连接到输出端（OUT）的晶体管（Q5和Q6）和基极连接在放大器的输入端（IN）上。 驱动级的pnp晶体管（Q5）的发射极通过第二恒流发生器（G2）连接到电源的正端子（vdd），并连接到电源的npn晶体管（Q1）的基极 输出级，并且驱动级的npn晶体管（Q6）的发射极通过电流镜电路的输出支路的npn晶体管（Q4）连接到电源的负极（gnd），并且 输出级的pnp晶体管（Q2）的基极。 放大器具有非常低或零偏移（Vos = Vout-Vin）。